Subject: On chip Active termination

From: Prasad Rau <[email-masked]>
Date: Fri, 13 Apr 2001 17:57:40 -0700

Hi,

On our current design we support several standards using controlled impedance. By using this scheme
we can mimic driver or receiver end terminations for standards like SSTL,HSTLs
and GTL. The onchip termination is done using active devices as opposed to passive
elements.  For example in the SSTL2 Class I the parallel termination is at the receiver end.
Using the controlled impedance scheme we can eliminate the series & parallel termination resistor son the board.
I have created seperate IBIS models for the output and the input. When I use the output model
and drive the input model through a Tline using the HyperLynx tool I am not seeing the right
levels at the receiver end. It is telling me that the termination at the receiver is missing. I know
that the input IBIS model makes sense because if I look at the GND clamp curve I observe ~ 0mA
current at 1.3V ( which is the valid voltage level with the output tristated). The same driver model
if it drives a non controlled impedance receiver with the appropriate board termination at the receiver
gives me the correct levels at the receiver.

 Is HyperLynx unable to recognize onchip termination input IBIS models ? Has aynone
worked with controlled impedance and have suggestions in modelling them in IBIS.

Appreciate your help in this regard.

Thanks in advance,

Regards,

Prasad Rau
Xilinx

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From: "Matthew Flora" <[email-masked]>
Date: Sat, 14 Apr 2001 11:00:43 -0700

Dear Prasad Rau,

Might I suggest that you ask technical support for the HyperLynx products at
[email-masked] or (425) 869-2320?

Best regards,
Matthew Flora