Subject: IBIS component generation, PECL differential inputs, analog I/O pins, Vmeas, Cref, Rref, Vref

From: Roland Chang <[email-masked]>
Date: Thu, 12 Jun 1997 10:40:54 -0700

Hello, I am using s2ibis2 and HSPICE netlists to generate IBIS files.  I
am using s2ibis2 to first generate IBIS models  for the inidividual
"types" of pins, and then cutting and pasting the [Model] portion of the
individual IBIS pin models into a larger "main" IBIS file which
describes the entire component.  This saves having to set up s2ibis2 for
generating the entire component all at once.  Once created, I can use
and reuse IBIS pin models for pins on the component that are identical
in nature.  Is there any problem with the IBIS model generation scheme
I've outlined above?  I would especially like to hear from other people
who have worked with s2ibis2 and SPICE to create their IBIS models.

Secondly, I am now faced with how to setup both the s2ibis2 *.s2i file
and the IBIS file for some PECL (Pseudo-ECL) differential inputs.  Has
anyone had to generate IBIS models for pins that are both differential
and Pseudo-ECL(or ECL) before?  How does s2ibis2 handle the [Diff pin]
Keyword, and associated pin list section? In the s2ibis2 manual, it says
that no processing is actually performed on the [Diff pin] list.  Does
this mean that I could create a single ECL input pin first using
s2ibis2, include the [Model] section of the single ECL input IBIS file
into a 'main' IBIS file for a component, connect the model name to
appropriate pins on the component, and then add the [Diff pin] pin list
later in the actual 'main' IBIS file for the component?

Thirdly, how are analog I/O pins treated in IBIS and s2ibis2?  How would
I setup an analog I/O pin in s2ibis2 and IBIS?

And finally, are the Vmeas, Cref, Rref, Vref parameters used for
anything in s2ibis2, or in IBIS files?  (are they actually processed? or
are they just for reference)

Thanx for your time,

Roland

******************************************
Roland Chang ext. 2647

PMC-Sierra 
Applications Department
105-8555 Baxter Place
Burnaby, BC
V5A 4V7
Tel: (604) 415-6000

email: [email-masked]
******************************************

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From: Srinivas Gande <[email-masked]>
Date: Fri, 13 Jun 1997 12:30:21 +0531

Hi chang, 
	
	Included inline comments. Please someone  correct me, if I made
	any mistake. 

>  who have worked with s2ibis2 and SPICE to create their IBIS models.

	This is correct way of doing.  

>  later in the actual 'main' IBIS file for the component?

	For PECL & ECL:--

	In s2i define [Pullup Reference] and [Pulldown Reference] to VCC. 
	[Model type] to be of Ouput_ECL or  Input_ECL. Rest of the s2i is 
	simillar (Voltage Range not required). The vout variation for 
	pullup and pulldown from VCC to  VCC-2.2 . In IBIS tablular format 
	you refer to VCC.  I encountered a problem in using s2ibis2 for 
	PECL (5V) device. You can edit the *.spi files set up by s2ibis2 
	and use [iterate] option to process SPICE input files in accordance 
	with specs. I also found problem in tabulating IBIS file by reading *.out
	files.  

	[Diff pin] is not processed by s2ibis2.  It's right to add [Diff] 
	section at the end.  

>  I setup an analog I/O pin in s2ibis2 and IBIS?

	Scope of IBIS is restricted to analog behaviour of Digital ICS. 
	I am not sure what you really mean by analog I/O pin ?. 	
>  are they just for reference)

	No they are not used.  This information is reference
	for IBIS based simulators.   

..srinu

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From: [email-masked] (Syed Huq)
Date: Fri, 13 Jun 97 15:53:24 PDT

Hi Roland,

I can share with you my experience regarding your first question.
I have developed IBIS models from HSPICE using the s2ibis2 and I
did exactly what you described. With this approach of translating 
individual 'types' of pins, you can solve problems easily if
they occur. But, as you pointed out, you do have to put all
the individually run models back into 'ONE' entire IBIS model.
The parser test will help you debug if any manual errors were
introduced during the cut and paste.

I believe the Vmeas, Cref, Rref, Vref are for timing information
for the simulator only.

Regards,
Syed
National Semiconductor Corp.

> From [email-masked] Thu Jun 12 12:10:52 1997
> From: Roland Chang <[email-masked]>
> To: "[email-masked]'" <[email-masked]>,
>         "[email-masked]'"
> 	 <[email-masked]>
> Subject: IBIS component generation, PECL differential inputs, analog I/O pins, Vmeas, Cref, Rref, Vref 
> Date: Thu, 12 Jun 1997 10:40:54 -0700
> X-Mailer:  Microsoft Exchange Server Internet Mail Connector Version 4.0.994.63
> Content-Type> : > text/plain> ; > charset="us-ascii"> 
> Content-Transfer-Encoding: 7bit
>

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From: Andy Ingraham <[email-masked]>
Date: Sun, 15 Jun 97 17:44:15 EDT

> 	I am not sure what you really mean by analog I/O pin ?. 	

On a mixed-signal IC, analog pins would not have models in the IBIS
file.

It seems like one might use "NA" as the model_name under the [Pin]
keyword, to signify that these pins have no available IBIS data. 
However, that is not allowed.  Instead, use "NC".  Technically
incorrect, but it tells the IBIS parser to skip those pins.

[Pin]   signal_name     model_name      R_pin   L_pin   C_pin
|
  1     RAS0#           Buffer1         200.0m  5.0nH   2.0pF
  2     RAS1#           Buffer2         209.0m  NA      2.5pF
  3     Analog_out      NC
...

Regards,
Andy Ingraham