Subject: SPICE Convergence Tricks - Consequences?

From: Roland James Chang <[email-masked]>
Date: Tue, 20 May 1997 13:02:00 -0700 (PDT)

Once again, a big thanks to all who replied to my last question. :-)
I've been using several tricks to try to solve SPICE convergence
problems:

-adding a 0.001ohm resistor in seris with the stimulating source
-increasing the value of the ITL1 to 300-500. (more iterations allowed)
-relaxing ABSTOL
-decreasing the sweep of the stimulus (I couldn't quite get this one to
work)

Many people mentioned that convergence problems are quite common, I would
like to know how common are they?

Furthermore, I am curious if anyone has a convergence fix that works
everytime, as it seems tedious to try to get things to converge everytime
just by trial and error fixes.

Also, what kinds of side-effects, or problems (in terms of IBIS
modelling) have people encountered by forcing the analysis to converge via
fancy SPICE tricks?

One last question regards clarification about typ, min, and max
curves.  When one is generating curves for the typical case,
suppose the typical case passes but both the min and max fail, the columns
should read NA for min and max right? Now should I go back and try to
tweak the min and max to converge? OR are some curves meant to only work
for the typical case? 

Many thanks in advance,
Regards,

roland

*************************************************************************
*Roland Chang                          | email: [email-masked]           *
*Simon Fraser University               |        OR                      *
*School of Engineering Science         |        [email-masked]  *
*3rd year Computer Engineering Option  |                                *
*************************************************************************

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From: Andy Ingraham 21-May-1997 0823 <[email-masked]>
Date: Wed, 21 May 97 08:31:00 EDT

> like to know how common are they?

Depends greatly on the semiconductor models, and on whose SPICE you
are using.  Everyone gets them eventually.

> just by trial and error fixes.

You will never find a magic fix that works every time.  Well, I
suppose you could fully relax ABSTOL and the other *TOL parameters to
the point that SPICE just doesn't care about accuracy anymore; but
even then it might have convergence problems of a different nature.

There are all sorts of things lurking in SPICE simulations that cause
misconvergence.  Some may be called bugs in SPICE itself, or in the
semiconductor model equations and algorithms (such as discontinuities
in the formulas).  Others are artifacts of how we discretely sample a
continuous world, and how computers manipulate data.

Generally speaking, though, a few convergence tricks may work for most
problems you encounter with one set of semiconductor models.  Now if
your simulations involve models from several different vendors, then
SPICE may keep you on your toes.

> modelling) have people encountered by forcing the analysis to converge via

A general observation, not specific to IBIS modeling:  The results of
ANY SPICE simulation are never gospel.  Whether you use no "tricks" or
you use several, the results are just as circumspect.  Helping SPICE
converge can make its results more accurate, or less accurate. 
(Relaxing ABSTOL by orders of magnitude probably does not make it more
accurate.)

I have had SPICE simulations that converged to the wrong result (off
by several volts!), when no "tricks" were used.

Some of these "tricks" are already built into SPICE itself.  The SPICE
developers tailored its algorithms and parameters to give reasonable
results over a set of benchmark circuits they had.  The small resistor
in series with voltage sources is already used by SPICE to aid convergence
when you force initial conditions via the .NODESET or .IC statements.

> tweak the min and max to converge? OR are some curves meant to only work

Min and max curves ought to represent the extremes of what your device
will do.  If you can't get these by measurement or simulation, and you
care about having a model that shows those extremes, you need to
approximate, by whatever means possible.

If the best you can do is to shift the typ curves some amount,
up/down/left/right, it'll do.

Personally, I'd try to get the simulations to work.  Maybe this
problem points to something fundamentally wrong with the models
themselves, which could make even the typ curves wrong.

Regards,
Andy Ingraham

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From: [email-masked] (Zheng SHI)
Date: Wed, 21 May 97 10:18:45 PDT

in my experince, the convergence problems are often caused by 
the SPICE models of the clamping diodes, which have ideal value 
RS=0. because the I/V curve of the diodes is a pure exp() function,
SPICE doesn't converge with the extreme large diode current,
for example, 1e+20A.

          o VCC
          |
        -----
         / \   <-------RS=0
        /___\
I/O port  |
o---------o <------Voltage Range:(-2*Vpower to +2*Vpower)
          |
        -----
         / \   <-------RS=0
        /___\
          |
          |
          o VEE or GND