Subject: convergence problem

From: Sagheer Ahmad <[email-masked]>
Date: Mon, 16 Nov 1998 15:30:42 -0800

I am trying to do IBIS modeling of my output buffer  (vdd= 3,3.3,3.6 volt). While simulating,
using hspice for getting pull-up data, circuit does't converge for DC as well as TRAN analsis (beyond
3.8volt and below -2volt of out voltage). 

And it looks correct that output buffers should not converge (if there are no clamp/ESD diodes) in those
conditions. If that happens that what should I should. Should I truncate the pull-up range (-vdd to vdd*2) 
to -2v to 3.8v only. Or there is some other solution possible.

Please help me out. I am stuck.

Thanks in advance,
Sagheer at Interra.

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From: Kellee Crisafulli <[email-masked]>
Date: Mon, 16 Nov 1998 16:59:17 -0800

If you have exhaused methods to fix the model in HSPICE you might consider 
the following:

  Do your best to extrapolate the likely values.  If the HSPICE model works
within the range for which the chip is most likely to operate then
the only time this data is needed is if a circuit uses the model out side this
range (i.e. abnormal case).  The simulator that uses the IBIS model needs
to know
what to do so it doesn't have the same problem that HSPICE did.  Typically you
might consider a linear extrapolation of the last valid data.  Or if you
have a "feel" for this device you might know for example it is likely to
saturate
and roll off.  You might than include a best guess and roll off the current.

Best wishes..
Kellee

>Please help me out. I am stuck.
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Have a great day....
Kellee Crisafulli at HyperLynx
SI,EMC,X-talk and IBIS tools for the Windows platform
E-mail: <mailto:[email-masked]>
web:    <http://www.hyperlynx.com>
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