Subject: Re: standard loads on 66 MHz PCI

From: Gregory R Edlund <[email-masked]>
Date: Mon, 9 Nov 1998 18:06:35 -0500

I wonder if this is really a non-issue?  Does the somewhat "unusual" passage in
the PCI spec about Tval loading necessarily mean that the vendor datasheet for
that component must use the same loads?  Couldn't the vendor specify a
"traditional" standard load in the datasheet and still comply with PCI?

The real concern here is that the load used by the simulator to compute net
delays be IDENTICAL to the one specified in the datasheet.  Now, if component
datasheets are really using the three new PCI loads, then we truly have a
problem.  Beside the Motorola SRAM example, does anyone know of any PCI
components that actually use all three loads in the datasheet?

How new are these Tval loads?  Version 2.2 (currently in draft, dated June
1998)?

Greg Edlund
Advisory Engineer, AS/400 System Timing
IBM
3650 Hwy. 52 N, Dept. HDC
Rochester, MN 55901
[email-masked]

---------------------- Forwarded by Gregory R Edlund/Rochester/IBM on 11/09/98
04:44 PM ---------------------------

[email-masked] on 11/09/98 10:20:22 AM
Please respond to [email-masked]
To: [email-masked]
cc:
Subject: Re: standard loads on 66 MHz PCI

We had a similar problem with a Motorola MPC750.  The L2 cache MAX timing
numbers are specified to a 20pF load and the MIN numbers to a 5pF load.
We were using ICX to analyze timing.  We looked at the output under no load,
then at 20pF and 5pF.  The delta was measured to be 477ps.  We then adjusted
the timing sheets in ICX so that the minimum allowed routing distance was
effectively increased by 477ps to compensate for the additional 'test' load.
This allowed us to use a single IBIS model with Cref set at 20pF.  You may
be able to apply a similar 'trick' with the PCI driver and Vref.

David Haedge
Raytheon Systems Company

---

From: "Richard A. Schumacher" <[email-masked]>
Date: Tue, 10 Nov 1998 10:02:58 CST

> "traditional" standard load in the datasheet and still comply with PCI?

How do you demonstrate compliance in all corner cases with a 
single load datasheet? Especially if that single load is not
_any_ of those given in the design spec? Any device which 
complies in one corner case may comply in the others, or it 
may not. PCI takes the right approach in explicitly specifying 
the corner cases. It's up to customers to demand appropriate 
data sheets and models.  

Is it feasible to expand the IBIS model spec and build enough 
intelligence into the simulators so that together they can 
automatically simulate all the corner cases in a given design? 
That would be required to meet the logic designers' expectation 
for a plug-and-chug solution. (Most SPICEs have monte carlo
capabilities for such work; they require manual intervention
to set parameter limits et cetera, but at least they don't 
require a different model for each loading case. With a model 
consisting of multiple sets of I-V and V-T curves, one per 
loading case, there's more scope for error: knowing that the 
set for one case is correct does not tell the user whether the 
other sets are correct.)