Subject: Re: fwd: Re: [SI-LIST] : Does IBIS describe output transition which both MOS turned on?

From: "A. D. Shirpadaraj" <[email-masked]>
Date: Wed, 13 May 1998 13:29:49 +0531 (IST)

Hi Jean,

V-T curve implicitly contains the behaviour of a buffer
during transition. If you want to know the magnitude of 
current passing through the transistors during transition,
then it may not be possible from IBIS data directly.

                  ^ VDD
                  |
               ___|
        |------|  
        |      |__
        |         |
--  ----|         |-------0-----/\/\/\-----0VREF
  \     |         |       |
   \___ |      ___|       |
        -----o|         ----- 
              |__       -----
                 |        |
                 |        |  
                  --------0
                       ___|___
                        _____
                          _

   During transition  current being drawn(or sunk) from Vref
varies continously, which will be reflected in the output waveform.
So in that way V-T curve does capture transition behaviour of a buffer.

If you have more than one V-T curve, the transition can be modelled
more accurately.

Thanks

Shripadaraj
Cadence Design Systems
NOIDA
India

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From: Jean-Claude Perrin <[email-masked]>
Date: Wed, 13 May 1998 08:52:37 -0700

Vinu,

   This is not really true. The V/T curve in the IBIS model definition does not
give any information about the PMO/CMOS overlapped current.
The V/T describes the behavior of the buffer  output versus frequency but does
not give any information on the current passing internaly through the output
transistors.
To know the value of the through current it is necessary to know the "Ron"
variation of the two transistors during the transition periode. The value of
this current depends upon the equivalent impedance of the two transistors,
impedance which is connected between Vdd and Vss power supply.  
 
 Jean Claude Perrin

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Original text

From: Vinu Arumugham <[email-masked]>, on 5/12/98 10:56 PM:
To: John Lin - TAO <[email-masked]>
Cc: "'IBIS_USER'" <[email-masked]>, "'SI_LIST'" <[email-masked]>

John,

IBIS models also have V/T curves.  These should cover overlapped
conduction.

Vinu

John Lin - TAO wrote:

> Dear IBIS fans/SI Experts,
>
> As I know  for a CMOS device, during output transition, both PMOS and
> NMOS will turn on in a short period of time. I wonder if an IBIS model
> describes this behavior. If yes  then how it does. Will the behavior
> affect the accuracy of simulation with IBIS model?
>
> Based on what I know the V-I curve for PULL UP or DOWN is obtained by
> turning one MOS off and then swift the V-fixture to get Current reading.
> It seems to me that the V_I curve doesn't contain the information to
> describe the transition, both PMOS and NMOS turned on.
>
> Any comment?
>
> Thanks,
>
> JOHNLIN
> CAE Engineer of EDA Department
> Digital Equipment Corp. Taiwan Branch
> Email: [email-masked] <mailto:[email-masked]>
> TEL: 1-886-3-3900000 ext. 2152

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