Subject: Re: About WARNING of ibischk2

From: [email-masked] (Syed Huq)
Date: Mon, 6 Apr 1998 10:29:29 -0700

Hi,

I have been following this discussion regarding the parser WARNING
messages for V/T tables and have one comment.

>From a bench measured IBIS model, the DC V/I data is taken on
a testjig that is always different from the AC testjig. Also,
as expected, the DC and AC measurements are taken on different
equipments(DC on Curve Tracer, AC on Scope).

Knowing all these, the 2% WARNING on the parser does not make
much sense for V/T tables generated from measurements. Which 
means you may be violating this 2% rule all the time.

This check of the parser is ok for a SPICE translated model as the
same model was used for the V/I and V/T data.

What I would like to know is since this is a WARNING and not an
ERROR, how concerned does the model developer need to be ??

Regards,
Syed
National Semiconductor Corp.

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From: Chris Rokusek <[email-masked]>
Date: Mon, 06 Apr 1998 11:25:37 -0700

Hi,

Perhaps the ability to set the % used in the check should be allowed.  I
recall that we discussed this before...

Or, perhaps the 2% should be increased to 5%.  What percentage would
allow these measured models to pass with some headroom? 

Chris

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From: Matthew Flora <[email-masked]>
Date: Mon, 06 Apr 1998 11:42:17 +0000

Syed,

>ERROR, how concerned does the model developer need to be ??

Would changing the warning message around so that it gave the percentage
difference help?  (Currently, it just says that the difference is more
than 2%.)  Then the user could easily decide if the amount of mismatch is
acceptable.  In this way, someone that expects or is comfortable with a 5%
(or more) difference could ignore the warning.  (The program could still use
2% as the trigger for the warning.)

We could even expand the message beyond 2 lines of text to include a
description of how these numbers are generated.  I admit that many of
IBISCHK's messages are a bit too terse.

Regards,
Matthew Flora
Senior Engineer
HyperLynx
(425) 869-2320 PH
(425) 881-1008 FAX
[email-masked]

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From: Chris Rokusek <[email-masked]>
Date: Mon, 06 Apr 1998 11:38:47 -0700

Syed,

> ERROR, how concerned does the model developer need to be ??

When the warning is issued the model developer should determine the
cause of the warning as you have done (i.e. small discrepency due to
measurement technique) and then move on.  This is just a warning.

EDA tools: 

Viewlogic/Quad tools will use the VI curves as the basis for simulation
with the V/T waveforms as additional information so it turns out that a
small errors like 5% on waveform endpoints will **potentially** only
change simulation results on the order of uVolts (or not at all!) (DC
stable states remain same regardless of V/T waveforms).  I think most
EDA tools will operate in a similar manner.

The point of the warning is to let model developer know that something
major may be wrong like:

    They used a TYP VI curve with a MAX VT waveform
    They forgot to include a high curve!!
    They forgot to include a low curve!!
    They used a different load resistor than specified.
    The AC waveform wasn't done stabilizing at end of simulation.
    ...etc...

Any of the above would cause significant error so want to avoid.

Chris Rokusek
Viewlogic.