Subject: RE: C_comp Confusion

From: "Muranyi, Arpad" <[email-masked]>
Date: Wed, 31 Mar 1999 08:25:38 -0800

Rob,

C_comp is everything that you see when you look into the chip at the pad.
That includes pad capacitance, metal capacitance, transistor parasitics,
and everything you can think of.

Does this answer your question?

Arpad
=========================================================================

-----Original Message-----
From: Robert Goodrich [mailto:[email-masked]]
Sent: Wednesday, March 31, 1999 7:13 AM
To: [email-masked]
Subject: C_comp Confusion

OK, just when I think I know what C_comp is supposed to be I am led to
suspect a misunderstanding.  At the risk of asking a stupid question - I
think it is important for me to know the "bottom line" definition since
I am currently creating models for use by our customers.  The ver3_2
spec. (and previous versions) define C_comp as Si die capacitance.  From
the terminator model (and cookbook) I have assumed that meant the DC
capacitance to GND (substrate) looking at the actual pad (pad meaning
metal actually deposited on Si) for a given I, I/O, O etc. looking into
the placed and routed buffer.  From other sources (classes, people,
email) I keep hearing C_comp referred to as "component" Si die
capacitance.  This was recently described to me as total Si "chip"
capacitance.  Now, I don't know what that means - but it doesn't sound
like my assumption.  Is my understanding of what C_comp is supposed to
represent correct?

Thanks,
--Rob
--

Rob Goodrich
Circuit Design - Advanced Imaging Technology (AIT)
Motorola SPS, I&E Solutions
6501 William Cannon Drive West MD: OE37
Austin, TX 78735
[email-masked]
(512) 895-7341

---

From: "Robert Goodrich" <[email-masked]>
Date: Wed, 31 Mar 1999 11:10:21 -0500

Yes it does - and thanks, now I don't have to change any of my models . . .
--Rob

--

Rob Goodrich