Group B Issues

Discussion

There is general interest in alignment with SystemVerilog where possible. (However, it is not clear that the SystemVerilog LRM defines these details.) Being consistent with VHDL (e.g., s'last_value) is also desirable. In VHDL, all signals are considered to have been stable for infinite time into the past, so s'last_value is defined to return s at time 0. Similarly, prev(s) should return the initial value of s, and prev(s,clk) at the first tick of clk should return the initial value of s.

Resolution

1. Prev(s) == initial value of s at time zero.
2. Prev(s,clk) == initial value of s at the first tick of clk
3. Given the definition of Prev(s), then unclocked rose/fell are False at time 0
4. Prev() should apply to all variables in the expression that is its argument, so prev(v(i)) means evaluate v(i) at the previous time point, and similarly prev(f(i)) means evaluate f(i) at the previous time point (i.e., given prev(i) as the input).
5. Note that if function f has side-effects (particularly, memory), then prev(f) may be undefined
6. In all of the above cases, we should check that this is consistent with SystemVerilog definitions

Further Discussion

LRM Changes

• First Draft
• Second Draft
• Third Draft

Note that these changes need to be coordinated with the Group A changes.