Group F Issues

Discussion

For issue 15, the Extensions SC seemed to feel that this should be addressed in the IEEE 1076 VHDL working group rather than in the IEEE 1850 PSL working group. Specifically, the VHDL LRM should define what implicit declarations of the logical operators are made, and for what types. For issue 17, the Extensions SC agreed to adopt the 'strict' approach of defining a specific return type for each of the built-in functions when invoked in a VHDL context. For issue 27, the Extensions SC agreed to adopt the proposed change.

Resolution

1. for Built-in functions that return PSL Number, return VHDL type universal_integer
2. for prev(s), return the VHDL type of s
3. for Built-in functions that return a PSL Boolean, return VHDL type STD.Standard.Boolean
4. for endpoints, return VHDL type STD.Standard.Boolean
5. clarify that STD.std_logic_1164.std_ulogic'('H') is interpreted as True
6. clarify that STD.std_logic_1164.std_ulogic'('L') is interpreted as False
7. clarify that this interpretation occurs at the top level of a Boolean expression, i.e., to the result of a Boolean used immediately within a PSL construct.

Additional Notes

• The return type of built-in functions and endpoints in a VHDL context is relevant both in the modeling layer (e.g., when rose() or an endpoint instance is used directly in VHDL code) and in the Boolean layer (e.g., when rose() or an endpoint instance is used in a VHDL expression that is a Boolean or a clock expression).

LRM Changes

• First Draft
• Amended First Draft