[$ieee-1850] Missing PSL features

Hello all

I am Jari Kalinainen form Nokia. I will be attending on IEEE P1850 developement as a end user from now on.
We have been using PSL for a quite long time now and there are two things that we would like to see in PSL standard.

First is the parametrization of signal names. Now if one wants to create reusable property library its nearly impossible to make it work with current parametrization support. If signal names (signals, vectors, integers) can be passed as parametrics we could have OVL type of reusable property sets which can be taken into use by just asserting correct property with your own signal names as parametrics.
I know that there have been discussion about parametrization but I just want to give one solution that will satisfy our needs.

Second is the internal varables. Basically to able to pass values inside property (for letf side to right side or in sequences for clock cycle to another). I think this kind of feature exist in SystemVerilog.

I have gone through the errata and think that its missing these two features (or then I missed those, it is quite hard read document :-)).

BR
/Jari Kalinainen
 jari.kalinainen@nokia.com
 +358 40 549 3822
Received on Tue Oct 19 00:13:59 2004