[$ieee-1850] SVA changes summary

Below is the summary of changes to SVA that took place in IEEE-P1800.

1) The only major change was made to property/sequence declaration formal
arguments. The formal arguments can now optionally specify data types of
formal arguments. The motivation behind this change was:
- to be aligned with the overall System Verilog data typing definitions
- to allow strongly typed code to provide better compiler/tool
capabilities, optimization and error detection.
- to extend the data types that can be passed to assertions. One may pass
an class object and activate a method of that class.
- to allow activations of properties through the DPI external interface
with correct data types.
- to allow a well defined interface to properties such that external users
do not pass arguments that provide undesirable behavior.
2) Clarification was made with regard to the usage of reset (disable iff)
as follows:
- resets are asynchronous
- reset expressions are evaluated using the current values of the operands
and not sampled values
- end point of a sequence can be used in reset expressions by using
.triggered method
- ended, matched and local variables are not allowed in reset expressions
- if sampled value functions are used in reset expressions, clock must be
explicitly specified for those functions
- formal semantics were modified to reflect that local variables do not
affect the evaluation of reset expressions
3) Many typo's in the text.
4) Correction of examples
5) Clarification text added

Surrendra

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Surrendra A. Dudani
Synopsys, Inc.
377 Simarano Drive, Suite 300
Marlboro, MA 01752

Tel: 508-263-8072
Fax: 508-263-8123
email: Surrendra.Dudani@synopsys.com
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Received on Tue Dec 21 10:36:40 2004