VHDL Issue Number:      2001

Language_Version:       VHDL-93
Classification:         Language Modeling Enhancement or Deficiency
Summary:                Resize not working in numeric_std.vhd  (1076.3)
Relevant_LRM_Sections:
Related_Issues:
Key_Words_and_Phrases:  resize
Authors_Name:           Robert Jacobson
Authors_Phone_Number:   781-890-4200 x3550
Authors_Fax_Number:
Authors_Email_Address:  jake@aaec.com
Authors_Affiliation:    Atlantic Aerospace
Authors_Address1:       470 Totten Pond Rd
Authors_Address2:       Waltham MA  02451
Authors_Address3:

Current Status:         VASG-Approved

Superseded By:

------------------------
Date Submitted:         30 March 2000
Date Analyzed:          28-Oct-04
Author of Analysis:     Peter Ashenden
Revision Number:        3
Date Last Revised:      09 May 2005

Description of Problem
----------------------

Description_of_Problem: Comment statement for function RESIZE (signed)
states that "when truncating, the sign bit is retained along with the
rightmost bit", yet actual code takes only rightmost bits.  MSB is ignored.

Proposed Resolution
-------------------
Proposed_Resolution: Is code bad or is the comment statement wrong????

VASG-ISAC Analysis & Rationale
------------------------------

The comment is correct and the code implements what is described by
the comment.

The function declaration and comment is:

  function RESIZE (ARG: SIGNED; NEW_SIZE: NATURAL) return SIGNED;
  -- Result subtype: SIGNED(NEW_SIZE-1 downto 0)
  -- Result: Resizes the SIGNED vector ARG to the specified size.
  --         To create a larger vector, the new [leftmost] bit positions
  --         are filled with the sign bit (ARG'LEFT). When truncating,
  --         the sign bit is retained along with the rightmost part.

The body of the function, annotated with statement numbers, is:

  function RESIZE (ARG: SIGNED; NEW_SIZE: NATURAL) return SIGNED is
    alias INVEC: SIGNED(ARG'LENGTH-1 downto 0) is ARG;
    variable RESULT: SIGNED(NEW_SIZE-1 downto 0) := (others => '0');
    constant BOUND: INTEGER := MIN(ARG'LENGTH, RESULT'LENGTH)-2;
  begin
    if (NEW_SIZE < 1) then return NAS;                   -- 1
    end if;
    if (ARG'LENGTH = 0) then return RESULT;              -- 2
    end if;
    RESULT := (others => ARG(ARG'LEFT));                 -- 3
    if BOUND >= 0 then                                   -- 4
      RESULT(BOUND downto 0) := INVEC(BOUND downto 0);   -- 5
    end if;
    return RESULT;                                       -- 6
  end RESIZE;

Truncation occurs when NEW_SIZE < ARG'LENGTH.  In this case, BOUND is
initialized to NEW_SIZE-2, which equals RESULT'LENGTH-2.  This is the
index of the bit to the right of the sign bit in the result.

If NEW_SIZE is 0, statement 1 returns an empty vector for the function
result.

If the argument vector is empty, statement 2 returns an all-zero
vector for the function result.

Otherwise, statement 3 assigns to RESULT a vector, all of whose
elements are the sign bit of the argument vector.  Then statement 4
checks whether there are other bits to the right of the sign bit in
the result.  If so, statement 5 assigns to those bits the
corresponding rightmost bits of the function argument, without
overwriting the sign bit in the result.

If the submitter's implementation behaves other than as described
above, the implementation is in error.


VASG-ISAC Recommendation for IEEE Std 1076-1993
-----------------------------------------------

No change to 1076 or 1076.3.


VASG-ISAC Recommendation for Future Revisions
---------------------------------------------

The packages currently in 1076.3 are being incorporated into the next
revision of 1076 and extended in that context.  Extensive tests and
reviews of functionality will be done.


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