VHDL Issue Number:      2003

Language_Version:       VHDL-93
Classification:         Language Modeling Enhancement or Deficiency
Summary:                Specification of multi-cycle paths
Relevant_LRM_Sections:  None (as far as I can make out)
Related_Issues:
Key_Words_and_Phrases:  multi-cycle, synthesis
Authors_Name:           Joe Robinson
Authors_Phone_Number:   +441173129392
Authors_Fax_Number:     +441173129978
Authors_Email_Address:  joer@bri.hp.com
Authors_Affiliation:    Hewlett Packard
Authors_Address1:       Filton Road, Stoke Gifford
Authors_Address2:       Bristol, BS34 8QZ
Authors_Address3:       England

Current Status:         Forwarded

Superseded By:

------------------------
Date Submitted:         25 July 2000
Date Analyzed:
Author of Analysis:
Revision Number:        $Revision$
Date Last Revised:      $Date$

Description of Problem
----------------------

Handling of multi-cycle delays within VHDL.  Apologies if this is
being handled by one of the other SIGs (e.g. the synthesis support
group).

    It is a common requirement to specify paths within a synchronous
design which are multi-cycle, e.g. for a large addition operation. This
is typically done by describing a single cycle operation, including
control logic which only validates the results a multiple of cycles
later.  This path is then specified to the synthesis tools, which will
take the extra cycles into account whilst trying to meet timing for
this path.

    My problem with this is twofold:

    1. The simulator will have no concept of the multi-cycle nature of
this path, and will provide the correct result on the next clock
cycle. This leads to complications in verifying the control logic.

    2. There is an unnecessary additional step in describing a functional
requirement to the synthesis tool.

    I realise that this is strictly speaking a synthesis timing and
behavioural modeling issue, but think that as it is principle
describing synchronous design functionality, it is best handled at the
HDL RTL level.  

Proposed Resolution
-------------------
Specification of the multi-cycle path directly at the HDL RTL level,
with a clause similar to the 'after' which specifies the number of
cycles for the operation, defaulting to 1.  This would allow the
simulator to simulate this functionality at RTL to verify the control
logic), and could be supported directly by the synthesis tool vendors
to avoid the additional step of describing design functionality within
a synthesis script.

VASG-ISAC Analysis & Rationale
------------------------------
This is not an ISAC issue. It has been forwarded to the VASG to determine
which group should deal with it.

VASG-ISAC Recommendation for IEEE Std 1076-1993
-----------------------------------------------
TBD

VASG-ISAC Recommendation for Future Revisions
---------------------------------------------
TBD


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