VHDL Issue Number:      2005

Language_Version:       VHDL-93
Classification:         Language Definition Problem
Summary:                sla operator behavior does not match typical hardware 
                        behavior
Relevant_LRM_Sections:  7.2.3 Shift operators
    
Related_Issues: 
Key_Words_and_Phrases:  Shift operator sla
Authors_Name:           Stephen Bailey
Authors_Phone_Number:   303-588-2001
Authors_Fax_Number:     303-652-1578
Authors_Email_Address:  stephen@srbailey.com
Authors_Affiliation:    Synopsys Inc.
Authors_Address1:       6664 Cherokee Ct
Authors_Address2:       Niwot, CO 80503
Authors_Address3: 
 
Current Status:

Superseded By:          2004

------------------------
Date Submitted: 7 August 100
Date Analyzed:
Author of Analysis:
Revision Number: $Revision$
Date Last Revised: $Date$

Description of Problem 
---------------------- 
NOTE: I entered this IR based on an email from Paul Graham of Cadence
(pgraham@cadence.com).
    
The definition of sla in the 1993 LRM is kind of weird.  It basically
preserves the parity bit of the left input:
    
        1 sla 1 == 3
    
etc.  I have never seen a computer opcode which implements this
function, though sll, srl, and sra opcodes are ubiquitous.

Proposed Resolution
-------------------
Why not just define sla to be the same as sll (as in Verilog)?

VASG-ISAC Analysis & Rationale
------------------------------
TBD

VASG-ISAC Recommendation for IEEE Std 1076-1993
-----------------------------------------------
TBD

VASG-ISAC Recommendation for Future Revisions
---------------------------------------------
TBD


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