VHDL Issue Number:      2009

Language_Version:       VHDL-93
Classification:         Language Modeling Enhancement or Deficiency
Summary:                New std package, containing compiler and target identification information
Relevant_LRM_Sections:  The suggested change would go in Chapter 14, Predefined Language Environment.
Related_Issues:
Key_Words_and_Phrases:  Compiler Identification, Predefined Language Environment
Authors_Name:           Allan Herriman
Authors_Phone_Number:   +61 3 9210 5527
Authors_Fax_Number:
Authors_Email_Address:  allan_herriman@agilent.com
Authors_Affiliation:    Agilent Technologies
Authors_Address1:
Authors_Address2:
Authors_Address3:

Current Status:         Forwarded

Superseded By:

------------------------
Date Submitted:         2 November 2000
Date Analyzed:          29-Oct-04
Author of Analysis:     Peter Ashenden
Revision Number:        2
Date Last Revised:      01-December-04

Description of Problem
----------------------

1. I often experience difficulties writing vhdl that works well in
both synthesis and simulation.  Eg, I usually have some extra checking
or logging (to file) code during simulation, but I don't want this
same code to be present during synthesis.

2. I often write code for multiple fpga targets, or for a single
target using multiple synthesis tools.  Usually the code needs to be
customised depending on which target & tool is being used.

I currently handle both issues by isolating the code that changes in a
separate entity (in a separate file), and then selecting which files
get compiled for a particular tool / target combination.  (I guess I
could also use different architectures, and a configuration to select
them, but adequate tool support for configurations is not widespread.)

Maintaining separate source code files for minor variations in code is
quite inefficient.

I would like to be able to handle the smaller differences by having
some sort of "compiler defined" constants that I can use in an if-
generate statement.

Eg.

    if compiler_target = simulation generate
      -- code intended for simulation only
      -- goes here
    end generate;

    if compiler_name = "@#&$%!!!" and
       compiler_version = "6.0.0" generate
      -- some evil hack to get around
      -- the problems with this tool
    end generate;

    if compiler_target = "Xilinx" generate
      -- Xilinx specific bits here
    end generate


Proposed Resolution
-------------------

The simplest way to handle this would be to create a new package which
contains some constants.  This package is provided by the vhdl tool
vendor.  For simulation tools, this would require the addition of a
single file.  For synthesis tools, this would need to be handled by
the tool itself, as some of the constants would change depending on
which target technology has been selected.

A possible name for the package would be "compiler" (in the "std"
library)

Some of the constants in the package could be: "compiler_target" -
either "Simulation" or the name of the target technology
"compiler_name" - the name of the synthesis or simulation tool
"compiler_version" - the version of the tool

VASG-ISAC Analysis & Rationale
------------------------------

The submitter requests features that allow a model to determine
aspects of the environment in which it is executed or interpreted.
Such features are within the scope of the VHDL-200x Environment group.


VASG-ISAC Recommendation for IEEE Std 1076-2002
-----------------------------------------------

No change.


VASG-ISAC Recommendation for Future Revisions
---------------------------------------------

The submitter's request should be forwarded to the VHDL-200x
Environment group for consideration.


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