VHDL Issue Number:      2011

Language_Version:       VHDL-2002
Classification:         Language Modeling Enhancement or Deficiency
Summary:                A package body should be able to consist of several files
Relevant_LRM_Sections:  2.6 Package bodies
Related_Issues:
Key_Words_and_Phrases:  package, body, design unit
Authors_Name:           Volker Hetzer
Authors_Phone_Number:   +49 (821) 804 4741
Authors_Fax_Number:     +49 (821) 804 2910
Authors_Email_Address:  volker.hetzer@fujitsu-siemens.com
Authors_Affiliation:    ECAD Support/SW development
Authors_Address1:       Buergermeister Ulrich Str. 100
Authors_Address2:       86199 Augsburg
Authors_Address3:       Federal Republic of Germany

Current Status:         Forwarded

Superseded By:          

------------------------
Date Submitted:         26 February 2001
Date Analyzed:          29-Oct-04
Author of Analysis:     Peter Ashenden
Revision Number:        1
Date Last Revised:      29-Oct-04

Description of Problem
----------------------

    The problem we've got is that we have large
    hierarchical designs, consisting of several (more
    than 100) large modules instantiating each other.
    Now, when we try to use more than one design as
    building block for a project it can happen that
    two different versions of a sub component go into
    the same project.
    The obvious solution is to have one package per
    design (when used as building block for another design)
    with just the top entity comprising the package
    entity.
    However, as our designs get large, they have to be
    reread in full whenever one component in the package
    changes, leading to overly long turnaround times.

Proposed Resolution
-------------------

    I would like to suggest that everything that can go into
    a package body does not need to be in one file.
    As an example, consider a entity/architecture pair
    and a hypothetical new keyword "go_into_package":

    use IEEE.std_logic_1164.all;
    go_into_package MyDesign;
    entity subcomponent ...end subcomponent;
    architecture x of subcomponent is ... end x;


VASG-ISAC Analysis & Rationale
------------------------------

The submitter appears to be confusing a number of VHDL terms,
specifically, "entity", "component", "package" and "library".  This
makes it hard to determine the real problem experienced by the
submitter and to understand his proposed resolution.

Notwithstanding that, it appears that the submitter is requesting a
new language feature to improve productivity.  That lies within the
scope of the VHDL-200x Modeling and Productivity group.


VASG-ISAC Recommendation for IEEE Std 1076-2002
-----------------------------------------------

No change.


VASG-ISAC Recommendation for Future Revisions
---------------------------------------------

Forward the submitter's request to the VHDL-200x Modeling and
Productivity group, with a suggestion that they contact the submitter
to seek clarification of his problem and proposed resolution.


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