VHDL Issue Number: 2012 Language_Version: VHDL-2002 Classification: Language Definition Problem Summary: VHDL lacks inherent statements to describe the most basic hardware design equations Relevant_LRM_Sections: Related_Issues: Key_Words_and_Phrases: Authors_Name: Weng Tianxiang Authors_Phone_Number: 818-998-0070 Authors_Fax_Number: 818-998-4459 Authors_Email_Address: wtx@umem.com Authors_Affiliation: Micro Memory Inc Authors_Address1: 9540 Vassar, Chatsworth CA 91311 Authors_Address2: Authors_Address3: Current Status: Forwarded Superseded By: ------------------------ Date Submitted: 6 April 2001 Date Analyzed: 29-Oct-04 Author of Analysis: Peter Ashenden Revision Number: 1 Date Last Revised: 03-December-2004 Description of Problem ---------------------- The most basic equation in hardware design: OutBus <= a * ABus + b * BBus + c * CBus + d * DBus + e * EBus; One statement structure in serial mode: if(a = '1') then OutBus <= ABus; elsif( b = '1') then OutBus <= BBus; elsif(c = '1') then OutBus <= CBus; elsif(d = '1') then OutBus <= DBus; elsif(e = '1') then OutBus <= EBus; end if; or in another equal form: if(a = '1') then OutBus <= ABus; end if; if(b = '1') then OutBus <= BBus; end if; if(c = '1') then OutBus <= CBus; end if; if(d = '1') then OutBus <= DBus; end if; if(e = '1') then OutBus <= EBus; end if; In concurrent mode: OutBus <= ABus when a = '1' else BBus when b = '1' else CBus when c = '1' else DBus when d = '1' else EBus; In those above 3 situations, a superfluous condition is posed on the equation, it means a priority tree is implied in all three situations. Actually most of time when dealing with main data flow, all above conditions are mutually exclusive, no need to pose the extra conditions on the final equation. The following is a resulting equation generated from a commercial software: OutBus <= (!d & !e & (CBus # !c)) & (c # b & BBus # !b & ABus) # (d & e & DBus) # e & EBus; When those conditions contained in the above equation are multi-items, the logic become much more complex and finally in my design for PCI core it become critical paths. In another words, due to using VHDL, users have to linguish the impest pattern to write the most basic equation. Finally I wrote a function like BoolAndVector(x: bool, y: std_logic_vector) return std_logic_vector; to do a * ABus; But finally it cannot resolve my problem either. The following real example from my design shows real difficulty I have seen facing and many VHDL users facing: SetLowAD_O1 : process(nRESET, CLK66M) begin if(nRESET = '0') then AD_O1(31 downto 0)<= (others=>'0'); elsif(CLK66M'event and CLK66M = '1') then if(TConfigReadEnable) then case ConfigPtr(7 downto 2) is when CONFIG_VENDOR_ID => -- 0x00 AD_O1(15 downto 0) <= VENDOR_ID; AD_O1(31 downto 16) <= DEVICE_ID; when CONFIG_COMMAND => -- 0x04 AD_O1(15 downto 0) <= ConfigCommand; AD_O1(31 downto 16) <= ConfigStatus; .... end case; elsif(TDMAPtrReadEnable) then AD_O1(2 downto 0) <= B"000"; case TDMAPtr(6 downto 3) is when DMA_BATTERY_MAGIC =>-- 0x00 AD_O1(7 downto 0) <= CSRMAGIC_NUMBER; AD_O1(31 downto 8) <= (others=>'0'); when DMA_EDC_LED => -- 0x08 AD_O1(7 downto 0) <= CSRLEDControl; AD_O1(31 downto 8) <= (others=>'0'); ... end case; end if; ... In the above example, all conditions are known to be mutually exclusive, and VHDL lacks a statement structure to handle the situation in a very simple way: either use the simplest way to express your idea as above, but get a very complex logic equations that would surprise its author, or you write it in very complex form to achieve the simplest equation you have in mind. Proposed Resolution ------------------- My suggestion to this problem is to introduce two new statement structures as follows: 1. for serial sector: IF conditionA THEN Statements; ELSOR conditionB THEN Statements; ELSOR conditionC THEN Statements; ELSE Statements; END IF; The resulting equation will be: OutBus <= ConditionA * AValue + ConditionB * BValue + ConditionC*CValue + not(ConditionA+ConditionB+...)*LastValue; The similar statement structure is for concurrent sector: OutBus <= ABus WHEN a ELSOR BBus WHEN b ELSOR CBus WHEN c ELSE DBus; The resulting equation will be OutBus <= a * ABus + b * BBus + c * CBus + not(a+b+c)* DBus; VASG-ISAC Analysis & Rationale ------------------------------ The submitter's requirement to be able to use scalar values to gate vector values is largely met by the VHDL-200x Fast Track proposal FT-3. In that proposal, logical operators will be provided with one operand being a scalar bit, boolean or standard-logic value and the other being a vector of the corresponding element type. Thus, the submitter's equation OutBus <= a * ABus + b * BBus + c * CBus + d * DBus + e * EBus; will be representable directly as the statement OutBus <= a and ABus or b and BBus or c and CBus or d and DBus or e and EBus; Beyond that, the submitter identifies a more general requirement to select among a number of sequential-statement lists based on general Boolean conditions that are known (or assumed or asserted) to be mutually exclusive. The VHDL-200x Modeling and Productivity group has a placeholder for a proposal to address this issue. As of the date of this analysis, no work has been done in that group on preparing a proposal. VASG-ISAC Recommendation for IEEE Std 1076-2002 ----------------------------------------------- No change. VASG-ISAC Recommendation for Future Revisions --------------------------------------------- Forward the submitter's request to the VHDL-200x Modeling and Productivity group for consideration. -------------END OF IR----------------