VHDL Issue Number: 2014 Language_Version: VHDL-2002 Classification: Language Modeling Enhancement or Deficiency Summary: Allowance of the keyword "all" in place of a sensitivity list is desirable Relevant_LRM_Sections: 8.1 Wait Statement 9.2 Process Statement Related_Issues: Key_Words_and_Phrases: sensitivity list Authors_Name: Geoff Bull Authors_Phone_Number: +61 2 48711254 Authors_Fax_Number: +61 2 48711465 Authors_Email_Address: gbull@acenet.com.au Authors_Affiliation: none Authors_Address1: PO Box 1172 Authors_Address2: Bowral NSW 2575 Authors_Address3: Australia Current Status: Forwarded Superseded By: ------------------------ Date Submitted: 22 April 2002 Date Analyzed: 29-Oct-04 Author of Analysis: Peter Ashenden Revision Number: 1 Date Last Revised: 03-December-2004 Description of Problem ---------------------- When designing logic for synchronous circuits (e.g. rtl for asics) typically processes are used in just two ways 1. the sensitivity list contains just one signal, namely the clock. 2. the sensitivity list contains all input signals to the process The second case is used to define unclocked logic. Unfortunately, it is frequently the case that the user accidentally omits a signal from the sensitivity list and an unwanted latch is inferred. This problem can be difficult to debug. In addition, sensitivity lists present a code maintenance overhead - after modifying the logic for a process, the sensitivity list must be carefully checked. just one sign Proposed Resolution ------------------- that it should be permitted to use the keyword "all" as a sensitivity list. This would mean that the process is sensitive to all the signals used as inputs to the process. VASG-ISAC Analysis & Rationale ------------------------------ The VHDL-200x Fast Track group is addressing this enhancement request as part of FT-19. VASG-ISAC Recommendation for IEEE Std 1076-2002 ----------------------------------------------- No change. VASG-ISAC Recommendation for Future Revisions --------------------------------------------- Implement extensions developed in FT-19. -------------END OF IR----------------