VHDL Issue Number:      2015

Language_Version:       VHDL-93
Classification:         Language Definition Problem
Summary:                Generics should be able to incorporate other generics
Relevant_LRM_Sections:  4.3.2.1
Related_Issues:
Key_Words_and_Phrases:  interface list, interface object, declaration, generic
Authors_Name:           Brad Lichtenstein
Authors_Phone_Number:   781-481-9233
Authors_Fax_Number:     781-481-9234
Authors_Email_Address:  bjl@birger.com
Authors_Affiliation:    vhdl user
Authors_Address1:       38 Montvale Ave
Authors_Address2:       Suite 260
Authors_Address3:       Stoneham, MA  02180

Current Status:         Forwarded

Superseded By:

------------------------
Date Submitted:         7 May 2002
Date Analyzed:          29-Oct-04
Author of Analysis:     Peter Ashenden
Revision Number:        3
Date Last Revised:      05 January 2005

Description of Problem
----------------------

Reasonable example:
    entity E is
      generic(
        BUS_WIDTH : integer;
        DATA_ADDR : std_logic_vector(0 to BUS_WIDTH - 1);
    ....

    Presently, that is illegal.  Looping references surely should be
illegal, and it makes little sense to me for ports to be included in
other port definitions, etc---but generics are simply imported
constants (even if possibly unknown at compile time), and proscribing
their use in this fashion is similar to proscribing:

    ...
    constant MY_WIDTH    : integer := 5;
    constant MY_MAX_VALUE: integer := 2**MY_WIDTH - 1;
    ...

    Especially since it should be desirable to set the range of an
array generic --with another generic.


Proposed Resolution
-------------------

Change 4.3.2.1 to make an exception for generics that do not make
circular references.


VASG-ISAC Analysis & Rationale
------------------------------

(Note that Ada 95 does not allow the proposed relaxation:

"A name that denotes a formal parameter is not allowed within the
formal_part in which it is declared, nor within the formal_part of a
corresponding body...")

The VHDL-200x Fast Track group is developing a proposal to enhance
generics to allow generic types and subprograms.  As part of that
enhancement, it is proposed to allow a generic constant to be
referenced in a subsequent generic constant declaration in the same
generic list.  This change meets the requirements proposed by the
submitter, including avoiding circular definitions of generic
constants.


VASG-ISAC Recommendation for IEEE Std 1076-2002
-----------------------------------------------

No change.


VASG-ISAC Recommendation for Future Revisions
---------------------------------------------

Include the relaxation on use of generic constants within a given
generic list as part of the larger enhancement of generics proposed by
the VHDL-200x Fast Track group.


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