VHDL Issue Number: 2016

 Language_Version: VHDL-93
 Classification: Language Modeling Enhancement or Deficiency
 Summary: allowance of the keyword "all" in place of a sensitivity list is
esirable
 Relevant_LRM_Sections: 8.1 Wait Statement
     9.2 Process Statement
 Description_of_Problem: When designing logic for synchronous circuits
     (e.g. rtl for asics)
     typically processes are used in just two ways
     1. the sensitivity list contains just one signal, namely the clock.
     2. the sensitivity list contains all input signals to the process

     The second case is used to define unclocked logic.
     Unfortunately, it is frequently the case that the user
     accidently omits a signal from the sensitivity list
     and an unwanted latch is inferred. This problem can be
     difficult to debug.
     In addition, sensitivity lists present a code maintenance overhead
     - after modifying the logic for a process, the sensitivity list must
     be carefully checked.
     just one sign
 Proposed_Resolution: that it should be permitted to use the keyword "all"
     as a sensitivity list.
     This would mean that the process is sensitive to all
     the signals used as inputs to the process.
 Related_Issues:
 Key_Words_and_Phrases: sensitivity list
 Authors_Name: Geoff Bull
 Authors_Phone_Number: +61 2 48711254
 Authors_Fax_Number: +61 2 48711465
 Authors_Email_Address: gbull@acenet.com.au
 Authors_Affiliation: none
 Authors_Address1: PO Box 1172
 Authors_Address2: Bowral NSW 2575
 Authors_Address3: Australia
 irmail.pl: Submit Issue Report

 Current Status:

 1076-1993 Disposition:

 Disposition Rationale:

 Superseded By:	IR2014

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 Date Submitted: 22 April 102
 Date Analyzed:
 Author of Analysis:
 Revision Number: $Revision$
 Date Last Revised: $Date$

 Description of Problem
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 TBD

 Proposed Resolution
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 TBD

 VASG-ISAC Analysis & Rationale
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 TBD

 VASG-ISAC Recommendation for IEEE Std 1076-1993
 -----------------------------------------------
 TBD

 VASG-ISAC Recommendation for Future Revisions
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 TBD


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