VHDL Issue Number: 2017 Language_Version: VHDL-93 Classification: Language Definition Problem Summary: Generics should be able to incorporate other generics Relevant_LRM_Sections: 4.3.2.1 Description_of_Problem: Reasonable example: entity E is generic( BUS_WIDTH : integer; DATA_ADDR : std_logic_vector(0 to BUS_WIDTH - 1); .... Presently, that is illegal. Looping references surely should be llegal, and it makes little sense to me for ports to be included in other ort definitions, etc---but generics are simply imported constants (even if ossibly unknown at compile time), and proscribing their use in this fashion s similar to proscribing: ... constant MY_WIDTH : integer := 5; constant MY_MAX_VALUE: integer := 2**MY_WIDTH - 1; ... Especially since it should be desirable to set the range of an array eneric --with another generic. Proposed_Resolution: Change 4.3.2.1 to make an exception for generics that o not make circular references. Related_Issues: Key_Words_and_Phrases: interface list, interface object, declaration, eneric Authors_Name: Brad Lichtenstein Authors_Phone_Number: 781-481-9233 Authors_Fax_Number: 781-481-9234 Authors_Email_Address: bjl@birger.com Authors_Affiliation: vhdl user Authors_Address1: 38 Montvale Ave Authors_Address2: Suite 260 Authors_Address3: Stoneham, MA 02180 irmail.pl: Submit Issue Report Current Status: 1076-1993 Disposition: Disposition Rationale: Superseded By: 2015 ------------------------ Date Submitted: 7 May 102 Date Analyzed: Author of Analysis: Revision Number: $Revision$ Date Last Revised: $Date$ Description of Problem ---------------------- TBD Proposed Resolution ------------------- TBD VASG-ISAC Analysis & Rationale ------------------------------ TBD VASG-ISAC Recommendation for IEEE Std 1076-1993 ----------------------------------------------- TBD VASG-ISAC Recommendation for Future Revisions --------------------------------------------- TBD -------------END OF IR----------------