VHDL Issue Number:      2018

Language_Version:       VHDL-2002
Classification:         Language Modeling Enhancement or Deficiency
Summary:                Variable IN parameter should be no different than constant
Relevant_LRM_Sections:  2.1.1 Formal Parameters
Related_Issues: 
Key_Words_and_Phrases: 
Authors_Name:           Paul Graham
Authors_Phone_Number:   734-994-3223
Authors_Fax_Number:     734-994-3223
Authors_Email_Address:  pgraham@cadence.com
Authors_Affiliation:    Cadence Design Systems
Authors_Address1:       430 S First St
Authors_Address2:       Ann Arbor, MI 48103
Authors_Address3: 

Current Status:         VASG-Approved

Superseded By:

------------------------
Date Submitted:         23 July 2002
Date Analyzed:          1-Nov-04
Author of Analysis:     Peter Ashenden
Revision Number:        3
Date Last Revised:      09 May 2005

Description of Problem
----------------------

    There appears to be no real difference between a variable IN
    parameter and a constant parameter. The only apparent difference
    is that a general expression cannot be associated as an actual
    with a variable IN parameter.


Proposed Resolution
-------------------

    It should be possible to associate a general expression as an
    actual with a variable IN parameter.  Or, more generally, a
    variable IN parameter should be defined to be identical to a
    constant parameter.


VASG-ISAC Analysis & Rationale
------------------------------

There are further distinctions between in-mode variable parameters and
constant parameters (which must be of mode in), including:

- variable parameters not allowed for functions

- type conversion and conversion functions are allowed in associations
  for variable parameters, but not for constant parameters

- constant parameters cannot be of or include access types

A further significant difference is that, for a composite variable
parameter, the LRM allows an implementation to pass the actual
parameter by reference.  This would be problematic if the result of
evaluating an expression were allowed as an acutal for an in-mode
formal variable parameter.  Variables have storage semantics, and so
reference makes sense.  Expressions have value semantics, so storage
would have to be dynamically allocated to store the value and create a
reference.  This runs counter to the VHDL conceptual semantic model.

In most places where data values are to be passed into a subprogram,
constant parameters can be used.  One place where an in-mode variable
parameter must be used, is to pass an access value to a subprogram.
Since a constant cannot be of or include access an type, a variable
parameter must be used, and, consequently, the subprogram must be a
procedure.  By making the parameter in-mode, The subprogram can read
the access value, but cannot update it, even though it can update the
designated variable.

In summary, while the submitter's suggestion has some merit, there are
subtle distinctions that are worth preserving.


VASG-ISAC Recommendation for IEEE Std 1076-2003
-----------------------------------------------

No change.


VASG-ISAC Recommendation for Future Revisions
---------------------------------------------

No change.


-------------END OF IR----------------