VHDL Issue Number:      2019

Language_Version:       VHDL-2002
Classification:         Language Modeling Enhancement or Deficiency
Summary:                Reading outputs from within architecture
Relevant_LRM_Sections:
Related_Issues:
Key_Words_and_Phrases:
Authors_Name:           Ben Cohen
Authors_Phone_Number:   310 7214830
Authors_Fax_Number:
Authors_Email_Address:  vhdlcohen@aol.com
Authors_Affiliation:    consultant / author
Authors_Address1:
Authors_Address2:
Authors_Address3:

Current Status:         Forwarded

Superseded By:

------------------------
Date Submitted:         19 February 2003
Date Analyzed:          1-Nov-04
Author of Analysis:     Peter Ashenden
Revision Number:        2
Date Last Revised:      05 January 2005

Description of Problem
----------------------

With the evolution of formal verification and Accellera Sugar Property
Specification Language (PSL), I feel that it is essential that VHDL
provides the capability to read the driving value of an OUT port, like
a buffer.  Sugar is used as the language by many formal verification
tools, and by simulation tools.  Cadence now supports Sugar in
NC-Sim. It is expected that Sugar PSL will eventually be an IEEE
standard.  In Sugar you can add the following in-line comments
(processed by a tool that handles Sugar):

     architecture X of Y is
     ..
     begin
       -- sugar property HANDSHAKE is
       -- always {bus_req} |=> {ack; data_enb; done};

     Meaning that if there is a bus request, then at the next cycle
there should be an acknowledge, followed by a data xfr, followed by
done.  Note the reading of the OUT ports bus_req, data_enb, and done.
The same property description is written that way for Verilog, which
can read OUT ports.  However, because of the VHDL restriction of
reading OUT ports, users must go through temporary signals local to
architecture, and use concurrent signal assignment to OUT ports.
Buffers have not really caught on yet, and legacy designs do not use
buffers.

     Bottom line, the need to read OUT ports is even more critical now
because of the integration of PSL, which deals with property
specification and application of formal verification and simulatable
properties



Proposed Resolution
-------------------

see above

VASG-ISAC Analysis & Rationale
------------------------------

The VHDL-200x Fast Track group is addressing this enhancement request
in FT-12

VASG-ISAC Recommendation for IEEE Std 1076-2003
-----------------------------------------------

No change.

VASG-ISAC Recommendation for Future Revisions
---------------------------------------------

Implement extensions developed in FT-12


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