VHDL Issue Number: 2021 Language_Version: VHDL-2002 Classification: Language Modeling Enhancement or Deficiency Summary: Dynamic hardware construct Relevant_LRM_Sections: Related_Issues: Key_Words_and_Phrases: Authors_Name: Steve Casselman Authors_Phone_Number: 818-970-1711 Authors_Fax_Number: na Authors_Email_Address: sc@vcc.com Authors_Affiliation: Virtual Computer Corporation Authors_Address1: Authors_Address2: Authors_Address3: Current Status: Forwarded Superseded By: ------------------------ Date Submitted: 26 February 2003 Date Analyzed: 1-Nov-04 Author of Analysis: Peter Ashenden Revision Number: 2 Date Last Revised: 05 January 2005 Description of Problem ---------------------- I see in under the testbench slide there is a proposal for dynamic process creation and destruction. I'm assuming that it is to save memory and other resources during a simulation. My work is in the FPGA world where dynamic hardware is a reality. You can load a design and then load over parts of that design creating and destroying hardware on demand. The problem is that there are only ad hoc tools that allow you to do this. Even the ASIC world as now starting to offer FPGA fabric as standard cells. I would like to propose that VHDL address this new capability. I think a dynamic hardware construct would make VHDL the de facto language for FPGAs Proposed Resolution ------------------- VASG-ISAC Analysis & Rationale ------------------------------ The proposal for dynamically created processes is intended to support construction of active objects in a complex testbench, rather than as a means of modeling reconfigurable hardware. However, the proposal to provide features for modeling reconfiguration of hardware warrants investigation. At this stage, it is not clear what the most appropriate language mechanisms might be. The world of dynamic reconfiguration is still immature. Further investigation would be needed to determine language design requirements. VASG-ISAC Recommendation for IEEE Std 1076-2003 ----------------------------------------------- No change. VASG-ISAC Recommendation for Future Revisions --------------------------------------------- The VHDL-200x SC should review the need for modeling dynamically reconfigurable systems and, if a need is identified, establish language design requirements. -------------END OF IR----------------