VHDL Issue Number:      2023

Language_Version:       VHDL-2002
Classification:         Language Modeling Enhancement or Deficiency
Summary:                Add predefined array types for integer, boolean, real and time
Relevant_LRM_Sections:  Chapter 14 (STD.STANDARD package)
Related_Issues:
Key_Words_and_Phrases:
Authors_Name:           Robert Ingham
Authors_Phone_Number:   unknown
Authors_Fax_Number:
Authors_Email_Address:  robert.ingham@candc.co.uk
Authors_Affiliation:    Communication & Control Electronics Limited
Authors_Address1:
Authors_Address2:
Authors_Address3:

Current Status:         VASG-Approved

Superseded By:

------------------------
Date Submitted:         6 March 2003
Date Analyzed:          1-Nov-04
Author of Analysis:     Peter Ashenden
Revision Number:        4
Date Last Revised:      09 May 2005

Description of Problem
----------------------

     I would like to see the following additional predefined array
     types:

         type    boolean_vector  is  array (natural range <>)    of  boolean;
         type    integer_vector  is  array (natural range <>)    of  integer;
         type    real_vector     is  array (natural range <>)    of  real;

     I have found these useful in developing verification models, and
     the 'boolean_vector' type useful in developing parameterized
     modules where the number of I/O sub-modules is passed in as a
     generic. I note that the 'boolean' type is now well supported for
     synthesis. It may be that

         type    time_vector     is  array (natural range <>)    of  time;

     is also of some merit.


Proposed Resolution
-------------------
TBD

VASG-ISAC Analysis & Rationale
------------------------------

Currently the types defined in package STANDARD for which there are
corresponding vector types are:

    BIT     (corresponding vector type is BIT_VECTOR)
    CHARACTER   (corresponding vector type is STRING)

The major types for which there are no vector types predefined are:

    BOOLEAN
    INTEGER
    REAL
    TIME

This excludes types such as SEVERITY_LEVEL and FILE_OPEN_MODE, which
are predefined for specific language constructs rather than for
modeling design data.

Given that types BOOLEAN, BIT and vectors of BOOLEAN and BIT elements
are all supported by the 1076.6 synthesis subset, it seems anomalous
that there is a predefined type for vectors of BIT elements but not
for vectors of BOOLEAN elements.  Hence, the proposal to predefine
BOOLEAN_VECTOR in package STANDARD has merit.

The type REAL_VECTOR is predefined in package STANDARD in 1076.1.
Making the type predefined in 1076 would enhance portability of design
units between the two language environments.

Were these vector types to be added, it would seem reasonable to add
vector types for INTEGER and TIME elements, if only for symmetry.

A concern that arises when adding types to package STANDARD is the
effect on legacy models, since all design units have an implicit use
clause that names all declarations in STANDARD.  Consider the effect
of adding a declaration of type BOOLEAN_VECTOR to STANDARD.

If a legacy model declares BOOLEAN_VECTOR in a design unit, the
model's declaration would remain directly visible in the design unit,
as a consequence of 10.4 a):

    a) A potentially visible declaration is not made directly visible
       if the place considered is within the immediate scope of a
       homograph of the declaration.

In this context, the relevant potentially visible declaration is
STANDARD.BOOLEAN_VECTOR.

However, if the model declares BOOLEAN_VECTOR in a package P and uses
P.all in a design unit, neither P.BOOLEAN_VECTOR and
STANDARD.BOOLEAN_VECTOR would be made directly visible in the design
unit, as a consequence of 10.4 b):

    b) Potentially visible declarations that have the same designator
       are not made directly visible unless each of them is either an
       enumeration literal specification or the declaration of a
       subprogram (either by a subprogram declaration or by an
       implicit declaration).

(The proposed change in VHDL-200x FT-01 does not affect this
situation, since it only deals with visibility of implicitly declared
subprograms, not explicitly declared types.)

So any legacy model that explicitly declares in a package a type of
the same name as one proposed to be added to STANDARD and that makes
that type visible in other design units through use clauses would no
longer be correct under the proposed change.  Such models would need
to be revised.

The decision on whether to add each of the proposed vector types to
STANDARD needs to trade off the effect on legacy models against the
benefit for newly developed models.  The trade-off may be different
for each type.  For example, the benefit of adding REAL_VECTOR to
achieve portability of models between VHDL and VHDL-AMS or of adding
BOOLEAN_VECTOR to better support synthesis may be greater than the
benefit of adding INTEGER_VECTOR or TIME_VECTOR.

In order to understand how concerned users might be about the effect
on legacy models, comments were sought on the comp.lang.vhdl
newsgroup.  There was little response, but those that did respond were
in favour of adding the types.


VASG-ISAC Recommendation for IEEE Std 1076-2002
-----------------------------------------------

No change.


VASG-ISAC Recommendation for Future Revisions
---------------------------------------------

Add the following declarations to the package STD.STANDARD:

    type BOOLEAN_VECTOR is array (NATURAL range <>) of BOOLEAN;

    type INTEGER_VECTOR is array (NATURAL range <>) of INTEGER;

    type REAL_VECTOR is array (NATURAL range <>) of REAL;

    type TIME_VECTOR is array (NATURAL range <>) of TIME;


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