VHDL Issue Number:      2025

Language_Version:       VHDL-2002
Classification:         Language Modeling Enhancement or Deficiency
Summary:                "Generate" for sequential code
Relevant_LRM_Sections:
Related_Issues:
Key_Words_and_Phrases:
Authors_Name:           Jim Lewis
Authors_Phone_Number:   503-590-4787
Authors_Fax_Number:
Authors_Email_Address:  Jim@SynthWorks.com
Authors_Affiliation:
Authors_Address1:
Authors_Address2:
Authors_Address3:

Current Status:         Forwarded

Superseded By:

------------------------
Date Submitted:         18 March 2003
Date Analyzed:          1-Nov-04
Author of Analysis:     Peter Ashenden
Revision Number:        0.2
Date Last Revised:      19-Jan-05

Description of Problem
----------------------

Think we may need conditional compilation for sequential code


Proposed Resolution
-------------------

Provide a mechanism to skip pieces of sequential code as if it never
existed).

Potentially relevant to VITAL libraries.  Ability to skip timing
checks, ... when simulating gates without timing.


VASG-ISAC Analysis & Rationale
------------------------------

For the purpose of this analysis, we assume conditional compilation to
be a mechanism for an analyzer (to use VHDL terminology) to exclude
parts of a VHDL description.

Before considering how a conditional compilation feature might be
provided, let us first review the need for conditional compilation,
since the submitter does not offer underlying reasons.

The submitter suggests that conditional compilation might be relevant
to VITAL libraries, allowing timing checks to be skipped if not needed
during a simulation.  However, such libraries are usually either
precompiled and provided in a library by an implementation, or are
built into an implementation.  The source code is usually not provided
to the user.  Hence, conditional compilation would not work for
removing the timing checks from the simulation.

More generally, the main motivator for conditional compilation is to
provide performance improvement in simulation without having to modify
source files.  Performance improvement can arise from a number of
effects, including:

- reduction in code and data size, affording better cache and register
  utilization

- eliminating aspect of code that prevent optimizations (eg,
  simplifying code to allow inlining of function calls)

- eliminating references to implicit signals, thus making net update
  simpler and faster

Some of the effect of conditional compilation in sequential may be
achieved simply with an if statement testing the value of a static
expression.  A code generator can perform dead-code elimination if it
knows the condition value.

However, a common use case would be to refer to a generic constant.
In that case, the condition would be globally static, not locally
static.  An implementation could only remove dead code in this case if
it performs optimization after elaboration.  Given that elaboration
already requires execution of parts of the model, most implementations
would already have performed code generation.  Hence, to be useful for
dead-code elimination, a condition would need to be locally static.

One form of locally static expression permitted in VHDL (see 7.4.1) is
a non-deferred constant explicitly declared by a constant declaration
and initialized with a locally static expression.  Such a constant may
be declared in a package and used throughout a model.  However, this
is a somewhat cumbersome approach.

Another issue is that most users would expect that the text excluded
by conditional compilation not be processed by an analyzer.  For
example, should the excluded text be syntactically or semantically
incorrect, the errors should not be processed.  This would not be the
case were if statements or generate statements used to exclude text,
as the nested statements within those constructs are analyzed and
errors detected.

To avoid analysis of potentially incorrect text, conditional exclusion
should be performed as part of lexical analysis of a description. This
might be done using directives to the analyzer, to be processed after
lexical analysis but before syntactic analysis.

The proposal for IP protection currently being considered by the
VHDL-200x Fast Track group also relies on analyzer directives that are
processed between lexical and syntactic analysis.  If directives for
conditional exclusion are to be developed, they should use the same
approach as directives for IP protection.  It would seem prudent to
develop a general mechanism for analyzer directives, and to define
specific directives for IP protection and conditional exclusion.


VASG-ISAC Recommendation for IEEE Std 1076-1993
-----------------------------------------------

No change.


VASG-ISAC Recommendation for Future Revisions
---------------------------------------------

The VHDL-200x Steering Committee should examine the requirement for
conditional compilation.  If there is a need, consideration should be
given to developing a mechanism based on analyzer directives, either
as part of the Fast Track effort or the Modeling and Productivity
effort.

In any case, the VHDL-200x Fast Track committee, in developing changes
to support IP encryption, should consider developing a general
mechanism for analyzer directives that can accommodate IP protection,
conditional compilation (if needed) and other future requirements.


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