VHDL Issue Number:      2033
Language_Version:       VHDL-2002
Classification:         Language Modeling Enhancement or Deficiency
Summary:                Incremental operator and auto subtype boundery wrap 
Relevant_LRM_Sections:  
Related_Issues: 
Key_Words_and_Phrases:  
Authors_Name:           Michel Verhaert
Authors_Phone_Number:   +3214252070
Authors_Fax_Number: 
Authors_Email_Address:  michel.verhaert@siemens.com
Authors_Affiliation:    
Authors_Address1:   
Authors_Address2:   
Authors_Address3:   

Current Status:         Not an ISAC issue

Superseded By:

------------------------
Date Submitted:         7 April 2004
Date Analyzed:
Author of Analysis:
Revision Number:        $02$
Date Last Revised:      $02 July 2004$

Description of Problem
----------------------

    Incremental operations on bitvectors have an embedded wraparound
    result when maximum value is reached.

    signal a :
    unsinged(1 downto 0);
    a <= a + 1; -- never needs to be constrained
    
    However an integer increment must always be constrained,
    e.g. otherwise a simulator will report an error: If 'a' would be
    an natural:

    signal a : natural range 0 to 3;
    a <= (a + 1) mod 4; -- must be explicitly constrained either with 
                        -- with a modulo operation or with a boundery test.
    
    if a = 3 then 
     a <= 0;
    else 
     a <= a + 1;
    end if;
    
    It gets even worse when the subtype does not start at 0, then the
    modulo operation may become complex and a test is the better way
    to resolve.
     
    Nevertheless this extra code is kind of silly work because we have
    explicitly defined the bounderies of the subtype.

Proposed Resolution
-------------------

    I would like to get rid of these brainless tests and let the
    simulator/synthesis tool resolve the bounderies themselves.

    Maybe a good way to do this is to introduce incremental operators
    that would auto resolve the integer subtype within its boundaries:

    One could take the ++/-- operators from C, overload the "+"/"-"
    operator by using only one param, or by using an inc/dec operator
    word:

    a <= a+; -- single param '+' overloading or ...
    a <= a++; -- the C operator
    a <= inc a; -- 
    variable a :
    natural range 0 to 5; 
    a := 5;
    a := a+; -- would resolve to a = 0;
    
    variable a : natural range 1 to 5; 
    a := 5;
    a := a+; -- would resolve to a = 1;
    
    a := 1;
    a := a-; -- would resolve to a = 5;
    
    In case "+" is overloaded coding mistakes would be more apparent:
    b := a+ + b;  -- result differs from  b := a+ b; 
    b := (a+) + b;
    b := a++ + b; -- is better
    b := inc a + b; -- is even better
    
    For uniformity this operator should also be overloaded by bit vector types. 

VASG-ISAC Analysis & Rationale
------------------------------
This is not an ISAC issue. It belongs to the Modeling and Productivity group
(if no  type changes need to be made to support this) or to the
Data Types and Abstraction group.

VASG-ISAC Recommendation for IEEE Std 1076-2002
-----------------------------------------------
TBD

VASG-ISAC Recommendation for Future Revisions
---------------------------------------------
TBD


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