VHDL Issue Number:      IR2034
Language_Version:       VHDL-2002
Classification:         Language Modeling Enhancement or Deficiency
Summary:                Introduce history attribute on signals to auto infer registers  
Relevant_LRM_Sections:  
Related_Issues: 
Key_Words_and_Phrases:  
Authors_Name:           michel verhaert
Authors_Phone_Number:   +3214252070
Authors_Fax_Number: 
Authors_Email_Address:  michel.verhaert@siemens.com
Authors_Affiliation:    
Authors_Address1:   
Authors_Address2:   
Authors_Address3:   
Current Status:         Forwarded

Superseded By:

------------------------
Date Submitted:         8 April 104
Date Analyzed:
Author of Analysis:
Revision Number:        $Revision$
Date Last Revised:      $Date$

Description of Problem
----------------------
Often extra signals need to be declared and assigned in order to detect changes
on them, which leads to additional coding effort and also readibility suffers 
from it.
    

Proposed Resolution
-------------------
    I propose the "hist and init" attributes to allow the VHDL tools to 
automatically infer the necessary registers and boolean logic.
    'hist results in a boolean, while 'init forces initialization of the 
signals history.
     
    Following example should auto infer a register to store the previous 
condition of 'a' and 
    the clock cycle when 'a' changes from any previous value 
(differing from '1') into '1',
     b will be a single cycle pulse when the event occurs
    
    entity a is
    port ( a :
    in;
           b : out;
           clk : in;
           res : in
    );
    -- VHDL today
    architecture RTL of test is 
    signal a_old : bit;
    begin
    process (clk, res) :
     begin 
       if res = '1' then
         a_old <= '0';
         b <= '0';
       elsif rising_edge(clk) then 
          a_old <= a;
          b <= '0';
          if a = '1' and a_old /= '1'  then 
             b <= '1';
          end if;
       end if;
     end process;
    end RTL;
    -- proposed enhancement
    architecture RTL of test is 
    begin
    process (clk, res) :
     begin 
       if res = '1' then
    -- the init attribute does not reflect the default state of signal a itself,
    -- but rather its inferred register preset state; 
    
         a'init <= '0';
         b <= '0';
       elsif rising_edge(clk) then 
          b <= '0';
          -- the 'hist param represents the value of 'a' itself
          if a'hist('1') then
             b <= '1';
          end if;     
       end if;
     end process;
    
    In case also the previous (stored) state needs to be equal to a specific 
value, then the 'hist attribute would contain an array in which the first 
element is the newest in time, the newest one in our case the initial signal 
'a' itself.
    
    'hist (signal, latest clocked, ....--->, oldest clocked value)
    
    
    -- VHDL today
          if a = '1' and a_old = 'L'  then 
    -- proposed enhancement
          if a'hist('1','L') then 
    
    When an history requires at least 2 specified values and the type is of a 
bit or std_logic type, 
    the syntax should allow for a vector notation. 
    
    a'hist("1L") is identical as a'hist('1','L')
    a'hist("1-") is identical as a'hist('1');
            
    The gain in code writing and readability becomes even more obvious in the 
example when an edge needs to be detected on an asynchronous signal.
    
    In the following example when 'a' is evaluated in a clocked process, the 
VHDL tool should infer 2 register stages prior to evaluation of the signal.
    Hence signal (port) 'a' is clocked 3 times , twice for synchronization, and
once for
    edge detection: the third register is compared with the second to check 
the change.
    
    Again, the 'init attribute presets the inferred registers to a know state.
    If required, 'init could be indexed:
    a'init(1) <= '0'; -- shift stage 1 --> newest value
    a'init(2) <= '0'; -- shift stage 2
    a'init(3) <= '1'; -- shift stage 3 --> last in time
    
    this is the same as a'init <= "001";
    
    -- VHDL today
    architecture RTL of test is 
    signal a_old : bit_vector(2 downto 0);
    begin
    process (clk) :
     begin 
       if res = '1' then
         a_old <= (others => '0');
         b <= '0';
       elsif rising_edge(clk) then 
          b <= '0'; 
          a_old <= a_old(1 to 0) & a;
          -- we don't care about the original signal and the first reclocked
          -- because we consider them asynchronous.
          if  a_old(1) = '1' and a_old(2) = '0' then 
             b <= '1';
          end if;
       end if;
     end process;
    end RTL;
    -- proposed enhancement
    architecture RTL of test is 
    begin
    process (clk,res) :
     begin 
       if res = '1' then
         a'init <= (others => '0');
         b <= '0';
       elsif rising_edge(clk) then 
          b <= '0'; 
          if a'hist("--10") then 
             b <= '1';
          end if;
       end if;
     end process;
    
    -- the attributes should span any type, here an example using integers:
    
    process (clk,res) :
     begin 
       if res = '1' then
         a'init <= (others => 0);
         b <= '0';
       elsif rising_edge(clk) then
          b <= '0'; 
          if a'hist(7, 5, 4) then 
             -- signal a = 7, a-1 = 5 and a-2 = 4
             b <= '1';
          end if;
       end if;
     end process;
    
    -- caution when used outside a clocked process:  history infers latches, 
    -- and the absolute time history is lost:
    
    a'hist("01100") --> only keeps track of actual changes and results to 3 
                    --states and 2 latches => ("010").

Note added by author: Beside the 'hist and 'init attributes, it might be 
interesing also to have some method to extract an element from the history, 
this way enabling more easy pipelining RTL.

VASG-ISAC Analysis & Rationale
------------------------------
This is not an ISAC issue and has been forwarded to the Modeling and
Productivity group.

VASG-ISAC Recommendation for IEEE Std 1076-1993
-----------------------------------------------
TBD

VASG-ISAC Recommendation for Future Revisions
---------------------------------------------
TBD


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