VHDL Issue Number:      2035
Language_Version:       VHDL-2002
Classification:         Language Modeling Enhancement or Deficiency
Summary:                new function "stages" automates piplining
Relevant_LRM_Sections:  
Related_Issues:         2034    
Key_Words_and_Phrases:  
Authors_Name:           Michel Verhaert
Authors_Phone_Number:   +3214252070
Authors_Fax_Number: 
Authors_Email_Address:  michel.verhaert@siemens.com
Authors_Affiliation:    
Authors_Address1:   
Authors_Address2:   
Authors_Address3:   

Current Status:         Forwarded

Superseded By:

------------------------
Date Submitted:         9 April 2004
Date Analyzed:
Author of Analysis:
Revision Number:        $Revision$
Date Last Revised:      $Date$

Description of Problem
----------------------
In order to run a design a speed, sometimes pipeplining needs to be introduced and tuning may take several 
synthesis iterations. FPGA foundries Xilinx and Altera have tools available for generating pipelined logic:
    muxes, adders etc...
    
    This method has several coding incoveniences though: 
    - the code becomes more complex because these functions are components to be instantiated,
    - extra interconnection signals need to be declared
    - the function needs to be taken away from the process to which it actually belongs, hence downgrading 
readability.
    - When tuning the pipeline, one has to run the tool again because the number of stages is not 
parametrizable.
    
    Very often the function is not a standard one so we have to provide the solution ourselves:
    1: reclocking the result several times and using register balancing option on the registers during 
synthesis, which means extra work to set the synthesis guidelines.
    2: making your own set of parametrizable modules
    3: embedding the pipeline by timeconsuming handcrafted fractioning of the operation into stages

Proposed Resolution
-------------------
Therefor I suggest the new function "stages" and only to be used after clocked statements.
    
    Syntax:
    result <= operation stages N;
    
    Where N must represent positive integer (1,2, ....) where N=1 means a null operation 
     
    examples:
       -- normal single stage assigment
       bit_a_s <= '0' WHEN reset = '1' ELSE
                sig_vector_b(conv_integer(sig_vector_c)) WHEN rising_edge(clk);
      
      --   is identical as 
       bit_a_s <= '0' WHEN reset = '1' ELSE
                sig_vector_b(conv_integer(sig_vector_c)) stages 1 WHEN rising_edge(clk);
    
     -- but the following line adds an extra register stage for resolving the mux
    
       bit_a_s <= '0' WHEN reset = '1' ELSE
                sig_vector_b(conv_integer(sig_vector_c)) stages 2 WHEN rising_edge(clk);
    
     -- the following line adds 2 extra register stages for calculating the addition
      
       vector_f_s <= (OTHERS => '0') WHEN reset = '1' ELSE (vector_d_s + vector_e_s) stages 3 
                                     WHEN rising_edge(clk);
    
    -- other examples:
    
       PROCESS (Clk_i, Res_i)
       BEGIN  -- PROCESS
          IF Res_i = '1' THEN                
             bit_a_s <= '0';
             vector_f_s <= (OTHERS => '0') ;
             bit_b_s <= '0';
             bit_c_s <= '0';
          ELSIF rising_edge(Clk_i) THEN      
             bit_a_s <= vector_b_s(conv_integer(vector_c_s)) stages 2;
             vector_f_s <= (vector_d_s + vector_e_s)  stages 3;
             bit_b_s <= '0';
    
             bit_c_s <= '0';
    
             IF ((A+C(i) = D) stages 2 AND E < F stages 3) then
                bit_b_s <= '1';
             END IF;
             -- or 
             IF ((A+C(i) = D) AND L > C) stages 3 then
                bit_c_s <= '1';
             END IF;  
             -- quality synthesis tools must be able to 
             -- "resource share" some of the logic
          END IF;
       END PROCESS;
    
    Obviously, tuning the pipeline is only a matter of changing N.
    
    Adding this feature to a simulator should be extremely easy.
    Also for a synthesis tool the automation of the operation should be quite easy, it only has to insert the 
required register stages, and use its already embedded register balancing algorithm to position the registers, 
or it can deduce parametrized functions from the code.

VASG-ISAC Analysis & Rationale
------------------------------
This is not an ISAC issue, but should be dealt with by Modeling and Productivity

VASG-ISAC Recommendation for IEEE Std 1076-2003
-----------------------------------------------
TBD

VASG-ISAC Recommendation for Future Revisions
---------------------------------------------
TBD


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