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VHDL Issue Number:      2045

Language_Version:       VHDL-2002
Classification:         Language Modeling Enhancement or Deficiency
Summary:                Add the ability to comment an entire block of code.
Relevant_LRM_Sections:  13.8 Comments
Related_Issues: 
Key_Words_and_Phrases:  comments
Authors_Name:           Jeremy Webb
Authors_Phone_Number:   707-577-3063
Authors_Fax_Number: 
Authors_Email_Address:  jeremy_w_webb@agilent.com
Authors_Affiliation:    Agilent Technologies, Inc.
Authors_Address1:       1400 Fountaingrove Pkwy.
Authors_Address2:       MS: 4UST
Authors_Address3:       Santa Rosa, CA  95403

Current Status:         VASG-Approved

Disposition Rationale:

Superseded By:

------------------------
Date Submitted:         20 October 104
Date Analyzed:          21-Oct-04
Author of Analysis:     Peter Ashenden
Revision Number:        2
Date Last Revised:      20 July 2005

Description of Problem
----------------------

Description_of_Problem: It would be nice to have the ability to
comment an entire block of code without having to enter the "--" on
every line.  This gets very tedious, even if you can use a text editor
to enter them for you.

Proposed Resolution
-------------------

Proposed_Resolution: Something similar to Verilog HDL's block comment:
"/*" and "*/".  Maybe "-*" to start the comment block and "*-" to end
the comment block; obviously there wouldn't be any quotation marks
just the hyphen and asterisk sign.

VASG-ISAC Analysis & Rationale
------------------------------

This would be a relatively minor addition to the lexical constructs of
the language and would provide value to users.

While one might argue that "-*" and "*-" as delimiters are in keeping
with the existing comment symbol, users may be more familiar with the
C/Verilog delimiters and prefer them.  Moreover, the C/Verilog
delimiters are visually clearer.

On some languages, block comments can be nested.  However, the
rationale for that appears to arise where the language has no
end-of-line delimited comments.  There does not appear to be much
advantage in nesting block comments in VHDL, and the cost would be
complexity in the lexical analyzer.  Hence, it would be preferable
for block comments in VHDL not to nest.

The C++ standard makes a note that the // characters have no special
meaning in /*...*/ comments, and that the /* and */ character pairs
have no special meaning in // comments.  VHDL LRM text describing
comments should include a similar note.


VASG-ISAC Recommendation for IEEE Std 1076-2002
-----------------------------------------------

No change.

VASG-ISAC Recommendation for Future Revisions
---------------------------------------------

Revise 13.8 to specify comments as described in the analysis.


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