VHDL Issue Number:      2046

Language_Version:       VHDL-2002
Classification:         Language Modeling Enhancement or Deficiency
Summary:                Type independent ports and subprogram parameters
Relevant_LRM_Sections:  ?
Related_Issues: 
Key_Words_and_Phrases:  type, ports, parameters, 
Authors_Name:           Espen Tallaksen
Authors_Phone_Number:   +47 32850952
Authors_Fax_Number: 
Authors_Email_Address:  espen.tallaksen@digitas.no
Authors_Affiliation:    
Authors_Address1:       Doelasletta 7
Authors_Address2:       3408 Tranby
Authors_Address3:       Norway

Current Status:         Forwarded

Superseded By:

------------------------
Date Submitted:         1 November 2004
Date Analyzed:          05 November 2004
Author of Analysis:     Chuck Swart
Revision Number:        1
Date Last Revised:      05 November 2004

Description of Problem
----------------------

    It should be possible to make general subprograms (functions or
procedures) and general modules (entities) that can be used with
multiple types, so that overloads or new variants would not be needed
unless really required.  E.g. subprogram to extend a vector with
hyphens and return the entry-type; - why multiple overloads.  or a
general queue entity for any type.  Why multiple variants for the same
functionality ?

Proposed Resolution
-------------------
TBD

VASG-ISAC Analysis & Rationale
------------------------------

These problems are being addressed by the Data Types and Abstraction
group.  This issue will be forwarded to that group.

VASG-ISAC Recommendation for IEEE Std 1076-2002
-----------------------------------------------
No change to the existing language.

VASG-ISAC Recommendation for Future Revisions
---------------------------------------------

There is a very need for general programs and general entities
as requested by the submitter.An example of a generic subprogram
is one which swaps two values. An example of a generic entity
is a mux. Peter Ashenden has supplied the following examples, which
show how these needs can be met by an enhanced generics proposal under
review by the Data Types and Abstraction group:

An example of a generic subprogram to swap the values of two variables is

  generic ( type T )
  procedure swap ( v1, v2 : inout T ) is
    variable tmp : T;
  begin
    tmp := v1;
    v1 := v2;
    v2 := tmp;
  end procedure swap;

This can be thought of as a kind of template for a subprogram, where the
actual type is provided in a subprogram instantiation.  For example:

  procedure int_swap is new swap
    generic map ( T => integer );

  procedure bv_swap is new swap
    generic map ( T => bit_vector );

  variable i1, i2 : integer;
  variable bv1, bv2 : bit_vector(31 downto 0);
  ...

  int_swap ( i1, i2 );
  bv_swap ( bv1, bv2 );

A formal generic type can be associated with any type for which
variable assignment is allowed and which has implicitly defined "="
and "/=" operators.  If other operations on the type are required,
they can be represented as formal generic subprograms passed along
with the type in the generic list.  See the enhanced generics proposal
for more details.

While a generic type could also be used in an entity, it would
probably be necessary to add a further restriction that the actual
type be one that is allowed for the type of a signal (ie, excluding
access types or composite types with an access-type subelement).  If
we did that, then the following is an example of a generic mux:

  entity mux is
    generic ( type T );
    port ( sel : in bit;
           i0, i1 : in T;
           z : out T );
  end entity mux;

  architecture simple of mux is
  begin
    z <= i0 when sel = '0' else
         i1;
  end architecture simple;

The entity would be instantiated in the normal way, but with an actual
type associated with the formal generic type.  The ports i0, i1 and z
of that instance would then be of the actual type provided for T.