-------------BEGINNING OF IR---------------- VHDL Issue Number: 2052 Language_Version: VHDL-2002 Classification: Language Modeling Enhancement or Deficiency Summary: path_name and instance_name don't deal with operator symbols Relevant_LRM_Sections: 14.1 Related_Issues: Key_Words_and_Phrases: path name, instance name, attribute, subprogram Authors_Name: Peter Ashenden Authors_Phone_Number: +61 (8) 8339 7532 Authors_Fax_Number: Authors_Email_Address: peter@ashenden.com.au Authors_Affiliation: Authors_Address1: Authors_Address2: Authors_Address3: Current Status: VASG-Approved Superseded By: ------------------------ Date Submitted: 28 January 2004 Date Analyzed: 03 February 2005 Author of Analysis: Chuck Swart Revision Number: 3 Date Last Revised: 09 May 2005 Description of Problem ---------------------- The definitions of the path_name and instance_name attributes refer to subprogram_simple_name. However, a simple_name is just an identifier, and does not cover operator symbols. The implication is that a path_name or instance_name attribute of a named entity declared within subprogram that overloads an operator is not defined. Proposed Resolution ------------------- In each of the full_path_instance_element and path_instance_element productions, add an alternative of the form subprogram_operator_symbol signature VASG-ISAC Analysis & Rationale ------------------------------ The problem which the submitter raises is genuine. The best solution is simply to replace simple_name signature in full_path_instance_element and path_instance_element with designator signature VASG-ISAC Recommendation for IEEE Std 1076-1993 ----------------------------------------------- Interpret the LRM as if the recommended change had been done. VASG-ISAC Recommendation for Future Revisions --------------------------------------------- Make the recommended change. -------------END OF IR----------------