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VHDL Issue Number:        2088

Language_Version          VHDL-2002
Classification            Language Modeling Enhancement or Deficiency
Summary                   Formatted I/O
Relevant_LRM_Sections     
Related_Issues            
Key_Words_and_Phrases     
Authors_Name              Amal Khailtash
Authors_Phone_Number      (613) 271-1101
Authors_Fax_Number        
Authors_Email_Address     Amal.Khailtash@edgewater.ca
Authors_Affiliation       
Authors_Address1          
Authors_Address2          
Authors_Address3          

Current Status:           Forwarded

Superseded By:

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Date Submitted:           29 March 2006
Date Analyzed:
Author of Analysis:
Revision Number:          0
Date Last Revised:        06 April 2006

Description of Problem
----------------------

Verilog has had great formatted I/O similar to C for a long time. In
FT5A, why not provide formatted I/O for all the built-in types and
also std_logic_vector, (un)signed values.  Something similar SNUG 2002
contribution for C-Library functions.

Proposed Resolution
-------------------


VASG-ISAC Analysis & Rationale
------------------------------

This enhancement request will be forwarded to the VASG.

VASG-ISAC Recommendation for IEEE Std 1076-2002
-----------------------------------------------
TBD

VASG-ISAC Recommendation for Future Revisions
---------------------------------------------

Forward to the VASG.


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