VHDL Issue Number:        2104

Language_Version          VHDL-2002
Classification            Language Modeling Enhancement or Deficiency
Summary                   Using a configuration to leave a design unbound
Relevant_LRM_Sections     
Related_Issues            
Key_Words_and_Phrases     
Authors_Name              Jim Lewis
Authors_Phone_Number      503-590-4787
Authors_Fax_Number        
Authors_Email_Address     jim@synthworks.com
Authors_Affiliation       SynthWorks VHDL Training
Authors_Address1          
Authors_Address2          
Authors_Address3          

Current Status:           VASG-Approved

Superseded By:

------------------------
Date Submitted:           9 November 2006
Date Analyzed:            15 November 2006
Author of Analysis:       Peter Ashenden
Revision Number:          3
Date Last Revised:        23 May 2007

Description of Problem
----------------------

Issue:

    If one portion of a design is being tested, it would be
    convenient, and perhaps have faster simulations, if I could remove
    unnecessary subblocks of the design temporarily.
    
    The problem is that if a design is not explicitly bound, then it
    automatically default binds the most recently compiled
    architecture.
    
    Currently what I do to work around this problem is create a blank
    architecture named dummy and configure it in a configuration:
    
    configuration Cfg_Uart4_LoopBack of TbMemIO is
      for Structural
    
        for U_MemIO :
    MemIO 
          use entity Lib_MemIO.MemIO (Dummy) ;
        end for ; 
    
      end for ; 
    end Cfg_Uart4_LoopBack ;
    

Proposed Resolution
-------------------

Create an explicit way to make a design unbound.  For example (for
intent, not syntax):
    
    configuration Cfg_Uart4_LoopBack of TbMemIO is
      for Structural
    
        for U_MemIO :
    MemIO 
          unbound ; 
        end for ; 
    
      end for ; 
    end Cfg_Uart4_LoopBack ;
    
    

VASG-ISAC Analysis & Rationale
------------------------------

VHDL already includes a feature that meets the submitter's
requirement. An entity aspect of the form "open" in a binding
indication specifies that the component not be bound. See 5.2.1.1. The
submitter's example can be written as:

    configuration Cfg_Uart4_LoopBack of TbMemIO is
      for Structural
    
        for U_MemIO : MemIO 
          use open ; 
        end for ; 
    
      end for ; 
    end Cfg_Uart4_LoopBack ;


VASG-ISAC Recommendation for IEEE Std 1076-2002
-----------------------------------------------

No change is needed.

VASG-ISAC Recommendation for Future Revisions
---------------------------------------------

No change is needed.


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