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VHDL Issue Number:        2106

Language_Version          VHDL-2002
Classification            Language Modeling Enhancement or Deficiency
Summary                   Desire preprocessor (macro/ifdef) support in VHDL
Relevant_LRM_Sections     None.
Related_Issues            
Key_Words_and_Phrases     macro, preprocessor, ifdef
Authors_Name              Andrew Leaver
Authors_Phone_Number      408-544-7209
Authors_Fax_Number        
Authors_Email_Address     aleaver@altera.com
Authors_Affiliation       Altera Corp.
Authors_Address1          101 Innovation Dr
Authors_Address2          San Jose, CA
Authors_Address3          95134

Current Status:           Forwarded

Superseded By:

------------------------
Date Submitted:           1 December 2006
Date Analyzed:            11 January 2007
Author of Analysis:       Chuck Swart
Revision Number:          1
Date Last Revised:        11 January 2007

Description of Problem
----------------------

VHDL has no standard macro preprocessor and no ifdef for conditional
compilation. The lack of an ifdef/endif is the most common
complaint. VHDL users can use M4 or CPP, but the lack of
standardization makes it difficult to ship VHDL code that uses
conditional compilation to other users. The conditional generate
statement already in VHDL does not solve this problem as it cannot be
applied to ports and other structures.

[Addition comments, slightly edited, from Andrew Leaver]

I am responsible for the VHDL (and Verilog) support for Altera's FPGA
synthesis tools, and of course I am very interested in this issue
:-). We have a large number of VHDL users; the question of
preprocessor support comes up fairly regularly, including from our
internal IP designers. Our Software Product Planning department is
pushing me to find a solution. The problem is not technical, of course
- it is quite easy to add preprocessor support to our VHDL
compiler. It is enough of an issue that I have been tempted to simply
pick a macro processor standard and add it to our VHDL support in the
next software release. However, I would much rather follow a standard
than try to set my own.

I understand that making language changes is non-trivial and it is
unlikely anything will happen quickly. However, even if there is a
clear intent to include a given form of macro preprocessor in a future
VHDL revision I could ship it in our tools in the near future.
Alternatively, if you can tell me for sure that this will not get
attention, or if it gets clearly rejected, that will also help me a
lot in my future decision making on preprocessor support.

Thanks for your consideration! If I can do anything to help push this,
please let me know.

Proposed Resolution
-------------------

As the VHDL-200X standard already is planning to use ` as a compiler
directive (for `protect), it would make sense to adopt the `define,
`undef `ifdef, `else, `elsif, `endif, `ifndef from the Verilog 2001
standard, and later minor extensions in the SV standard.
    
    Either the CPP or M4 macro languages would also be acceptable.

VASG-ISAC Analysis & Rationale
------------------------------

Virtually every vendor has been asked to support some capability such
as the submitter requests. One possible resolution of this issue,
suggested by this proposal, is not to add this to VHDL, but instead,
to recommend a "standard" macro processing language to be used to
pre-process the VHDL code.

VASG-ISAC Recommendation for IEEE Std 1076-2002
-----------------------------------------------

No change.

VASG-ISAC Recommendation for Future Revisions
---------------------------------------------

Forward as a requirement for future language revisions.

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