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VHDL Issue Number:        2108       

Language_Version          VHDL-2002
Classification            Language Modeling Enhancement or Deficiency
Summary                   Behavior of "wait" when condition is already true
Relevant_LRM_Sections     
Related_Issues            
Key_Words_and_Phrases     wait, condition, sensitivity
Authors_Name              Ajeetha Kumari
Authors_Phone_Number      +91-80-26591356
Authors_Fax_Number        
Authors_Email_Address     ajeetha@gmail.com
Authors_Affiliation       Contemporary Verif Consultants
Authors_Address1          Bangalore
Authors_Address2          
Authors_Address3          

Current Status:           Forwarded

Superseded By:

------------------------
Date Submitted:           8 December 2006
Date Analyzed:            11 January 2007
Author of Analysis:       Chuck Swart
Revision Number:          1
Date Last Revised:        11 January 2007

Description of Problem
----------------------

http://verificationguild.com/modules.php?name:  Forums&file=viewtopic&t=1539
    
    This sounds like IEEE 1647/E's sync vs. wait feature that users
    would like in VHDL.
    
    Also Verilog's wait behaves this way, so it is desirable to have this.
    
[Added note: It might be difficult to access the website without
joining the group, so I (Chuck Swart) will summarize the issue.

There are times when you want to execute a code fragment when a
certain condition is true--if its not true you want to wait until the
condition is true.  This situation produces the following coding
fragment:

if( not condition) then
    wait for condition;

Coding this might be troublesome if "condition" is a complicated
expression. End of added note]

Proposed Resolution
-------------------

On a second thought, if VHDL supports macro definition, this could be
easily worked around as:
    
      #define enhanced_wait(cond) {
       if (not cond) then
         wait cond;
       end if;
      }
    
    Pseudo-code, just to explain my suggestion.
    
    Thanks
    Ajeetha, CVC
    www.noveldv.com

VASG-ISAC Analysis & Rationale
------------------------------

This is clearly an enhancement.

VASG-ISAC Recommendation for IEEE Std 1076-2002
-----------------------------------------------

No action.

VASG-ISAC Recommendation for Future Revisions
---------------------------------------------

Forward as a requirement for future language revisions.


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