VHDL Issue Number:        2110

Language_Version          VHDL-2002
Classification            Language Definition Problem
Summary                   Implicit subtype conversions not defined
Relevant_LRM_Sections     The following subclauses specify when an implicit subtype conversion 
                          is performed:
                          3.2.1.1, 8.5.1, 8.12 (actually notes that it's not performed, 
                          though this is changed in VHDL-2007), 12.2.2, 12.3.1.4, 12.3.2.1, 
                          12.6.2.
                          Subclause 7.3.5 describes type conversions.
Related_Issues            
Key_Words_and_Phrases     implicit subtype conversion
Authors_Name              Peter Ashenden
Authors_Phone_Number      +61 414 709 106
Authors_Fax_Number        
Authors_Email_Address     peter@ashenden.com.au
Authors_Affiliation       Ashenden Designs
Authors_Address1          
Authors_Address2          
Authors_Address3          

Current Status:           Superseded by Bugzilla #174

Superseded By:

------------------------
Date Submitted:           15 March 2007
Date Analyzed:            02 May 2007
Author of Analysis:       Chuck Swart
Revision Number:          1
Date Last Revised:        02 May 2007

Description of Problem
----------------------

The subclauses listed above specify cases where an implicit subtype
conversion is performed. Presumably this is an implicit type
conversion in which the type mark denotes a subtype, though this is
not actually defined.
    
In any case, the rules for type conversions in 7.3.5, under list item
b), describe how the bounds and elements of the result of an
*explicit* type conversion to an array type are determined. There is
no statement of how the bounds and elements of the result of an
*implicit* conversion are determined. Presumably, the same rules
apply. But if that's the case, why does the LRM only mention explicit
conversions here?

Proposed Resolution
-------------------

Add text specifying that an implicit subtype conversion is an implicit
type conversion in which the type mark denotes the target
subtype. Also, add text specifying that the bounds and element values
of an implicit subtype conversion are determined the same way as for
an explicit type conversion.

VASG-ISAC Analysis & Rationale
------------------------------


VASG-ISAC Recommendation for IEEE Std 1076-2002
-----------------------------------------------
TBD

VASG-ISAC Recommendation for Future Revisions
---------------------------------------------
TBD