VHDL Issue Number: 0002 Classification: Terminology, Grammar, and Typographical Errors Language Version: VHDL-87 Summary: Repair for a variety of typographical/editorial errors. Related Issues: None. Relevant LRM Sections: 1.2.2, 1.3, 2.2, 2.3, 3.2.1.1, 3.3.1, 4.3.1.2, 4.4, 7.3.2.2, 7.3.5, 9.6.1, 9.7, 12.2, 12.2.1, 12.2.2, 12.2.4, 12.3.1.3, 13.4.2, B Key Words and Phrases: N/A Current Status: Approved 1076-1993 Disposition: Closed (All Issues Completely Addressed) Disposition Rationale: LRM was updated. Superseded By: N/A -------------------- Date Submitted: 1988/10/18 Author of Submission: Doug Dunlop (and many others) Author's Affiliation: Intermetrics Author's Post Address: 4733 Bethesda Ave #415 Bethesda, MD 20814 Author's Phone Number: (301) 657-3775 Author's Fax Number: Author's Net Address: dunlop%inmet.inmet.com@uunet.uu.net ---------------------- Date Analyzed: 1988/11/10 Author of Analysis: Doug Dunlop Revision Number: $Revision: 1.9 $ Date Last Revised: $Date: 1995/08/03 15:56:46 $ Description of Problem ---------------------- There are a number of typographical and editorial errors in the LRM (see below). Proposed Resolution ------------------- These should be corrected. VASG-ISAC Analysis & Rationale ------------------------------ Indeed these are typographical and editorial errors and should be corrected. VASG-ISAC Recommendation for IEEE Std 1076-1987 ----------------------------------------------- 1. The line in the example from LRM 9.6.1 on Page 9-12 that reads component COMP port(A,B : inout BIT); should read component COMP port(A,B : inout BIT); end component; This corrects illegal VHDL syntax. ---------- 2. The lines in the example from LRM 1.2.2 on Page 1-8 that read component Full_Adder port(X, Y, Cin: Bit; Cout, Sum: out Bit); should read component Full_Adder port(X, Y, Cin: Bit; Cout, Sum: out Bit); end component; This corrects illegal VHDL syntax. ---------- 3. The lines in the example from LRM 2.3 on Page 2-6 that read Check (Setup=>10 ns, D=>Bus, C=>Clk1); Check (Hold=>5 ns, D=>Bus, C=>Clk2); Check (15 ns, Bus, Clk); -- ambiguous if Data'Base = Clock'Base should read Check (Setup=>10 ns, D=>Wire, C=>Clk1); Check (Hold=>5 ns, D=>Wire, C=>Clk2); Check (15 ns, Wire, Clk); -- ambiguous if Data'Base = Clock'Base This corrects illegal use of a VHDL reserved word. ---------- 4. The line from LRM 7.3.5 on Page 7-12 that reads type_conversion ::= type_mark ( expression ) should be indented to match the other grammar productions appearing in the LRM. ---------- 5. In the glossary (Appendix B) on Page B-1, the entries for "alias" and for "aggregate" appear in the wrong order. The order of these two entries should be reversed. ---------- 6. The line in the example from LRM 1.3 on Page 1-10 that reads for StructureView should read for Structure_View This is a typographical error. ---------- 7. The line in the example from LRM 3.3.1 on Page 3-15 that reads variable NEXT : LINK := HEAD.SUCC; should read variable NXT : LINK := HEAD.SUCC; This corrects illegal use of a VHDL reserved word. ---------- 8. The line in the example from LRM 4.4 on Page 4-14 that reads type POSITIVE is INTEGER range 1 to INTEGER'HIGH; should read subtype POSITIVE is INTEGER range 1 to INTEGER'HIGH; This corrects illegal VHDL syntax. ---------- 9. The line in the example from LRM 9.7 on Page 9-14 that reads B : block should read Gen : block Similarly, the line in the same example that reads end block B; should read end block Gen; These corrections allow the signal B to be visible where it is referenced in example. ---------- 10. The last two paragraphs of LRM 2.2 on Page 2-5 are notes but are not identified as such. These two paragraphs should be preceded by the header (in italics) "Note:". ---------- 11. The last sentence of LRM 12.3.1.3 on Page 12-4 which reads Elaboration of a size constraint consists of the evaluation of the expression. should be deleted. Size constraints have been removed from the language. ---------- 12. Item 6 in LRM 7.3.2.2 on Page 7-11 that reads 6. As the expression defining the initial value of the drivers of one or more signals in an initialization specification, where the corresponding subtype is a constrained array subtype. should read 6. As the expression defining the default values of signals in a signal declaration, where the corresponding subtype is a constrained array subtype. ---------- 13. The definition of "resume" in the glossary reads A process that resumes is a given simulation cycle becomes ready to execute and will execute at the end of the given simulation cycle. but should read A process that resumes in a given simulation cycle becomes ready to execute and will execute at the end of the given simulation cycle. This is a typographical error. ---------- 14. The sentence in the glossary from the definition of "specification" that reads There are four kinds of specifications: attribute specifications, initialization specifications, configuration specifications, and disconnection specifications. should read There are three kinds of specifications: attribute specifications, configuration specifications, and disconnection specifications. ---------- 15. There are two definitions of "guarded signal" in the glossary. The second of these is more informative and thus the first definition should be removed. ---------- 16. The sentence immediately above the examples in LRM 13.4.2 on Page 13-5 that reads An exponent indicates the power of the base by which the value of the based literal with the exponent. is not well formed. It should be replaced with An exponent indicates the power of the base by which the value of the based literal without the exponent is to be multiplied to obtain the value of the based literal with the exponent. An exponent for a based integer literal must not have a minus sign. ---------- 17. The references to "generic map clause" and "port map clause" in the 7th, 8th, 9th, and 10th items in the list beginning in LRM 3.2.1.1 on Page 3-11 should be read "generic map aspect" and "port map aspect", respectively. ---------- 18. The four refences to "port map clause" in the paragraph beginning "If a subelement of a resolved signal of a composite type is ..." from LRM 4.3.1.2 on Page 4-6 should be read "port map aspect". ---------- 19. In LRM 12.2, 12.2.1, 12.2.2, and 12.2.4 on Page 12-2, the references to "generic map clause" and "port map clause" should be read "generic map aspect" and "port map aspect", respectively. There are two such references in 12.2, two in 12.2.1, one in the title of 12.2.2, one in the body of 12.2.2, one in the title of 12.2.4, and one in the body of 12.2.4. ---------- 20. The line in the example from LRM 1.3.2 on Page 1-13 that reads use entity StdCells.PadTriState4 (StdCells.DataFlow) should read use entity StdCells.PadTriState4 (DataFlow) This corrects illegal VHDL syntax. ---------- 21. The sentence in LRM 3.1.3.1 on Page 3-7 that reads The only predefined physical is type TIME. should read The only predefined physical type is TIME. This is a typographical error. ---------- 22. The sentence in LRM 3.1.3.1 on Page 3-7 that reads The range of TIME is implementation-dependent, but it is guaranteed to include the range -2147483647 to +2147483467. should read The range of TIME is implementation-dependent, but it is guaranteed to include the range -2147483647 to +2147483647. The writing of "46" for "64" is a typographical error. ---------- 23. The literals "-1E38" and "+1E38" in LRM 3.1.4.1 on Page 3-8 should be read "-1.0E38" and "+1.0E38", respectively. Similarly, the literals "-1E38" and "+1E38" in LRM 3.1.4 on Page 3-8 should be read "-1.0E38" and "+1.0E38", respectively. These changes make the type of these literals universal_real, which is the appropriate type for specifying the minimum bounds of floating point types. ---------- 24. The list item in LRM 4.3 on Page 4-3 that reads o a formal port of a design entity. should read o a formal port. The phrase "of a design entity" mistakenly prevents the list item from applying to block ports. ---------- 25. The line from the example in LRM 3.3 on Page 3-14 that reads type BUFFER_PTR is access BUFFER; should read type BUFFER_PTR is access MY_BUFFER; This corrects illegal use of a VHDL reserved word. ---------- 26. The example in LRM 1.3.2 on Page 1-13 that reads for D1 : DSP -- binding specified in design entity or else defaults for Filterer -- configuration items for filtering components end for; for Processor -- configuration items for processing components end for; end for; should read for D1 : DSP -- binding specified in design entity or else defaults for DSP_STRUCTURE for Filterer -- configuration items for filtering components end for; for Processor -- configuration items for processing components end for; end for; end for; This corrects a missing block configuration. VASG-ISAC Recommendation for Future Revisions --------------------------------------------- Correct these problems in the LRM.