VHDL Issue Number:      0007
Classification:         Language Definition Problem
Language Version:       VHDL-87
Summary:                The semantics of component configuration are in error.
Related Issues:         None.
Relevant LRM Sections:  1.3.2
Key Words and Phrases:  Component configuration
Current Status:         ISAC-Approved
1076-1993 Disposition:  Closed
Disposition Rationale:  Not available
Superseded By:          N/A
-----------------------
Date Submitted:         1989/02/04
Author of Submission:   Paul Menchini
Author's Affiliation:   CAD Language Systems, Inc.
Author's Post Address:  P.O. Box 13036
                        Research Triangle Park, NC  27709-3036
Author's Phone Number:  (919) 361-1913
Author's Fax Number:    
Author's Net Address:   mench@clsi.com
-----------------------
Date Analyzed:          1991/01/15
Author of Analysis:     Doug Dunlop
Revision Number:        $Revision: 1.9 $
Date Last Revised:      $Date: 1995/07/26 18:04:51 $


Description of Problem
----------------------
Paragraph 3 of Section 1.3.2 (on Page 1-12) reads:

        "It is an error if both an explicit configuration specification
         (in an architecture body) and a component configuration
         containing a binding indication (in a configuration
         declaration) apply to the same component instance."

The intent of this paragraph is to ensure that there are not multiple (and
possibly conflicting) bindings applicable to a given component instance.

However, it is possible to supply an explicit configuration specification that
does not imply any design entity, in which case, if a non-defaulted binding of
the component to a design entity is to occur, a component configuration
containing a binding indication is necessary.  This case is best illustrated
with an example:

        architecture A of E is
          component C
          end component;

          for all:C use open;   -- does not imply a design entity
        begin
          ...
        end A;

        configuration C of E is
          for A
            for all:C
              use entity CE (CA);
              ...
            end for;
          end for;
        end C;


Proposed Resolution
-------------------
Modify the above paragraph in the LRM to read:

        "It is an error if both an explicit configuration specification
         (in an architecture body) and a component configuration
         containing a binding indication (in a configuration
         declaration) apply to the same component instance unless the
         entity aspect of the configuration specification is _open_."

(The text "_open_" indicates that the text should be emboldened.)


VASG-ISAC Analysis & Rationale
------------------------------
We feel that the VHDL given above should be considered illegal. 
We do not recommend the "Proposed Resolution" above since the
present LRM seems clear on this matter and the proposed resolution
adds language complexity for relatively little gain.  Furthermore,
the suggestion would be further complicated if it considered the
similar situation where a design entity was implied but the
architecture body was not implied.  Finally, the proposed resolution
can be viewed as a way of "overridding" the "assertion" in the
architecture that the instance is open.  This is not consistent
with the language philosophy behind configuration declarations.


VASG-ISAC Recommendation for IEEE Std 1076-1987
-----------------------------------------------
We suggest taking the LRM literally with regard to this issue and
do not recommend an alternate interpretation.


VASG-ISAC Recommendation for Future Revisions
---------------------------------------------
There does not seem to be compelling reason to re-visit this issue
when the next version of the standard is being prepared.