VHDL Issue Number: 0028 Classification: Language Definition Problem Language Version: VHDL-87 Summary: Map aspects in component instantiation statements are badly defined. Related Issues: None. Relevant LRM Sections: 5.2.1.2 Key Words and Phrases: Component instantiation statement, port map aspect, generic map aspect Current Status: ISAC-Approved 1076-1993 Disposition: Closed (All Issues Completely Addressed) Disposition Rationale: Section 5.2.1.2 was revised. Superseded By: N/A ----------------------- Date Submitted: 1989/02/10 Author of Submission: Doug Dunlop Author's Affiliation: Intermetrics, Inc. Author's Post Address: 4733 Bethesda Ave #415 Bethesda, MD 20814 Author's Phone Number: (301) 657-3775 Author's Fax Number: Author's Net Address: dunlop@inmet.inmet.com ----------------------- Date Analyzed: 1991/01/11 Author of Analysis: Paul Menchini (mench@clsi.com) Revision Number: $Revision: 1.9 $ Date Last Revised: $Date: 1995/08/03 00:08:19 $ Description of Problem ---------------------- LRM Section 5.2.1.2 refers to "the immediately enclosing binding indication" and "the enclosing configuration specification." These are not defined in the case the port map aspect or generic map aspect appears in a component instantiation statement. Proposed Resolution ------------------- The paragraph beginning "The purpose ..." should be preceded by a clause that says it applies only if the map aspect appears in a binding indication. A paragraph should be inserted after it that applies only if the map aspect appears in a component instantiation statement. Its content should be as in If the map aspect appears in a component instantiation statement, its purpose is to associate actuals with the locals of the component referenced in the component instantiation statement. No local may be associated with more than one actual. VASG-ISAC Analysis & Rationale ------------------------------ The author assumes in his proposed resolution that the LRM merely fails to enumerate all the cases where a map aspect can appear. He rejects the interpretation that the paragraph at issue was intended to be applicable only to generic and port map aspects appearing in binding indications. The ISAC agrees that these interpretations are what was intended. VASG-ISAC Recommendation for IEEE Std 1076-1987 ----------------------------------------------- Paragraph 4 of Section 5.2.1.2 (on page 5-5), beginning with "The purpose ..." is intended to apply to generic map aspects and port map aspects appearing not only in binding indications, but also in component instantiation statements and in block statements. VASG-ISAC Recommendation for Future Revisions --------------------------------------------- Modify Paragraph 4 of Section 5.2.1.2 to read as follows. Text appearing in all-uppercase letters denotes text to be added; text surrounded by square brackets denotes text to be deleted. The purpose of port and generic map aspects IS AS FOLLOWS: * PORT AND GENERIC MAP ASPECTS APPEARING IMMEDIATELY WITHIN A BINDING INDICATION [to] associate actuals with the formals of the design entity interface implied by the immediately enclosing binding indication. Each local port or generic of the component instances to which the enclosing configuration specification applies must be associated as an actual with at least one formal. No formal may be associated with more than one actual. * PORT AND GENERIC MAP ASPECTS APPEARING IMMEDIATELY WITHIN A COMPONENT INSTANTIATION STATEMENT ASSOCIATE ACTUALS WITH THE FORMALS OF THE COMPONENT INSTANTIATED BY THE STATEMENT. NO FORMAL MAY BE ASSOCIATED WITH MORE THAN ONE ACTUAL. * PORT AND GENERIC MAP ASPECTS APPEARING IMMEDIATELY WITHIN A BLOCK HEADER ASSOCIATE ACTUALS WITH THE FORMALS DEFINED BY THE SAME BLOCK HEADER. NO FORMAL MAY BE ASSOCIATED WITH MORE THAN ONE ACTUAL.