VHDL Issue Number: 0029 Classification: Language Definition Problem Language Version: VHDL-87 Summary: The meaning of configuration declarations is unclear. Related Issues: 0027, 0072, 0112, 0145 Relevant LRM Sections: 1.3, 12 Key Words and Phrases: Configuration declarations Current Status: ISAC-Approved 1076-1993 Disposition: Bugs Fixed, Enhancements Outstanding (No ISAC Issues) Disposition Rationale: Non ISAC issues remaining. Superseded By: N/A ----------------------- Date Submitted: 1989/02/10 Author of Submission: Doug Dunlop Author's Affiliation: Intermetrics, Inc. Author's Post Address: 4733 Bethesda Ave #415 Bethesda, MD 20814 Author's Phone Number: (301) 657-3775 Author's Fax Number: Author's Net Address: dunlop@inmet.inmet.com ----------------------- Date Analyzed: 1991/01/22 Author of Analysis: Doug Dunlop (dunlop@inmet.inmet.com) Revision Number: $Revision: 1.9 $ Date Last Revised: $Date: 1995/08/03 15:58:54 $ Description of Problem ---------------------- Consider the following VHDL: entity E is generic(N : Positive); port(P : out Bit); end E; ------------------------------------------------------------------------------- use Work.E; architecture A of E is begin G1 : if N > 1 generate L:block signal S : Bit; component C generic(N : Positive); port(P : out Bit); end component; begin I:C generic map(N => N - 1) port map(P => S); P <= not S; end block; end generate; G2 : if N = 1 generate P <= '0'; end generate; end A; ------------------------------------------------------------------------------- use Work.E; configuration C1 of E is for A for G1 for L for I : C use entity E(A); end for; end for; end for; end for; end C1; ------------------------------------------------------------------------------- use Work.E; configuration C2 of E is for A for G1 for L for I : C use entity E(A); for A for G1 for L for I : C use entity E(A); end for; end for; end for; end for; end for; end for; end for; end for; end C2; 1 - Does configuration C1 cause all instances of component C to be associated with entity E(A) or just the first? 2 - If only the first, how can a user write a configuration that covers all the instances? 3 - If C1 covers all instances, is C2 an error because there are multiple implicit configuration specifications for the same instantiation statement? 4 - Is it an error if C2 is instantiated with N=2 or less? Proposed Resolution ------------------- These matters have been discussed in detail with CLSI. The following is our understanding of what configurations in the language mean at the present time. The answer to the first question is that C1 covers only the first instance. With respect to the second question, the user cannot write a configuration that covers all instances. The third question is not applicable. The answer to the fourth question is "no". More precisely, the configuration is allowed to reference instances that do not exist when the model is elaborated. This is an aspect of this that seems annoying but it is the only reasonable interpretation of the language. VASG-ISAC Analysis & Rationale ------------------------------ The root of the problem described in this IR is the conflict that can arise between the model as specified in the configuration and the model as it elaborates in accordance with its generate logic. The specification in the configuration is necessarily "static" and fixed at the time the configuration is written. Considerable more flexibility is allowed in the elaboration-time structure of the model due to the existence of generate statements. Short of allowing the equivalent of generate logic within a configuration declaration (or, alternatively, removing generate statements from the language), it seems unlikely this conflict can be resolved. With the language as currently specified, a configuration must "allow for" all possible elaboration-time executions (with respect to the generate logic in the model) if it is to be "general purpose". In terms of the example given above, the "depth" of the configuration declaration must match the maximum depth of recursion anticipated during elaboration (i.e., the maximum anticipated value of the generic parameter N). A clear implication of this is that it must be legal for a configuration to "reference" instances that do not materialize when the model is elaborated. These views correspond to those expressed in the proposed resolution above. VASG-ISAC Recommendation for IEEE Std 1076-1987 ----------------------------------------------- With respect to the four questions raised in the description of the problem: 1 - Only the initial instance of component C is associated with entity E(A). 2 - In theory it is possible to write a configuration that covers all the instances in the example by making it Positive'High "deep". This of course is not practical. 3 - N/A. 4 - It is legal (and often necessary) for a configuration to make reference to instances that are not created during the course of elaboration. VASG-ISAC Recommendation for Future Revisions --------------------------------------------- Investigate improvements to the configuration aspects of VHDL to eliminate or lessen the anomalies described above. One interesting possibility that should be considered is the notion of a a "self-recursive" configuration that could be used to configure all of the instances in the above example.