VHDL Issue Number: 0033 Classification: Language Definition Problem Language Version: VHDL-87 Summary: OUT/INOUT signal parameters are undefined in certain cases. Related Issues: Relevant LRM Sections: 2.1.1.2 Key Words and Phrases: Driver, signal parameter Current Status: Submitted 1076-1993 Disposition: Closed (All Issues Completely Addressed) Disposition Rationale: Superseded By: N/A ----------------------- Date Submitted: 1989/02/10 Author of Submission: Doug Dunlop Author's Affiliation: Intermetrics, Inc. Author's Post Address: 4733 Bethesda Ave #415 Bethesda, MD 20814 Author's Phone Number: (301) 657-3775 Author's Fax Number: Author's Net Address: dunlop%inmet.inmet.com@uunet.uu.net ----------------------- Date Analyzed: 1989/04/02 Author of Analysis: Doug Dunlop Revision Number: $Revision: 1.11 $ Date Last Revised: $Date: 1995/05/13 19:34:42 $ Description of Problem ---------------------- The semantics of INOUT and OUT signal parameters are defined in terms of driver association LRM 2.1.1.2. There are situations for which this definition is not applicable. For example, consider the case of a parameterless, package-resident subprogram X calling a subprogram Y and associating a signal (e.g., one declared in a package) with an OUT signal parameter of Y. There is no driver for the actual signal and the effect is undefined. It is highly likely the intention of the language designers was to disallow this. Proposed Resolution ------------------- In a subprogram call that occurs outside a process statement and that associates an actual signal with an OUT or INOUT formal signal parameter, the actual signal must itself be a signal parameter. VASG-ISAC Analysis & Rationale ------------------------------ As an illustration of this issue, consider the following VHDL fragment: entity e is procedure p1(...) is begin g <= ...; -- signal assignment to signal g end p1; procedure update(signal s : out bit); procedure p2(...) is begin update(g); -- call to update, passing signal g end p2; end e; In this VHDL, both procedures p1 and p2 update a signal named g, but only for procedure p1 is g required to be a procedure parameter (since the procedure is not contained within a process statement). The applicable LRM paragraph is from Section 8.3.1 which reads If a given procedure is declared by a declarative item that is not contained within a process statement, and a signal assignment statement appears in that procedure, then the target of the assignment statement must be a formal parameter of the given procedure or of a parent of that procedure, or an aggregate of such formal parameters. This paragraph indicates that it was a requirement on the language that the determination of which processes have drivers for which signals be computable at analysis time. The language, as pointed out in the statement of the problem, does not presently meet the requirement. It is very likely that drivers created by passing signals as parameters in subprogram calls were overlooked when the rules of LRM 8.3.1 were formulated. In particular, the above quoted LRM 8.3.1 sentence should probably have been followed by an additional sentence that read something like Similarly, if a given procedure is declared by a declarative item that is not contained within a process statement, and a signal is associated with an INOUT or OUT mode signal parameter in a subprogram call within that procedure, then the signal so associated must be a formal parameter of the given procedure or of a parent of that procedure. VASG-ISAC Recommendation for IEEE Std 1076-1987 ----------------------------------------------- The LRM should be read as though it contained the above additional sentence in LRM 8.3.1. VASG-ISAC Recommendation for Future Revisions --------------------------------------------- Add the new sentence to the LRM.