VHDL Issue Number:      0037
Classification:         Language Definition Problem
Language Version:       VHDL-87
Summary:                The disconnection-specification type mark is not
                        defined in one case.
Related Issues:         0063
Relevant LRM Sections:  5.3
Key Words and Phrases:  Disconnection specification, type mark
Current Status:         Superseded
1076-1993 Disposition:  Superseded (ISAC Issues Outstanding)
Disposition Rationale:  N/A
Superseded By:          0063
-----------------------
Date Submitted:         1989/02/10
Author of Submission:   Doug Dunlop
Author's Affiliation:   Intermetrics, Inc.
Author's Post Address:  4733 Bethesda Ave #415
                        Bethesda, MD  20814
Author's Phone Number:  (301) 657-3775
Author's Fax Number:    
Author's Net Address:   dunlop@inmet.inmet.com
-----------------------
Date Analyzed:          1990/10/02
Author of Analysis:     Paul Menchini (mench@clsi.com)
Revision Number:        $Revision: 1.10 $
Date Last Revised:      $Date: 1995/05/13 21:53:48 $


Description of Problem
----------------------
The LRM does not say what the type mark in a disconnection specification means
in the case a list of signal names is supplied.


Proposed Resolution
-------------------
We assume it is a form of redundancy and that the base type of each signal in
the list of signal names must be the same as the base type of the type mark.


VASG-ISAC Analysis & Rationale
------------------------------
This issue is considered in issue report 0063, which see.


VASG-ISAC Recommendation for IEEE Std 1076-1987
-----------------------------------------------
See issue report 0063.


VASG-ISAC Recommendation for Future Revisions
---------------------------------------------
See issue report 0063.