VHDL Issue Number: 0038 Classification: Language Definition Problem Language Version: VHDL-87 Summary: Evaluation of value expression in aggregates is unclear. Related Issues: Relevant LRM Sections: 7.3.2 Key Words and Phrases: Aggregate Current Status: Submitted 1076-1993 Disposition: Closed (All Issues Completely Addressed) Disposition Rationale: LRM covers this. Superseded By: N/A ----------------------- Date Submitted: 1989/02/10 Author of Submission: Doug Dunlop Author's Affiliation: Intermetrics, Inc. Author's Post Address: 4733 Bethesda Ave #415 Bethesda, MD 20814 Author's Phone Number: (301) 657-3775 Author's Fax Number: Author's Net Address: dunlop@inmet.inmet.com ----------------------- Date Analyzed: TBD Author of Analysis: TBD Revision Number: $Revision: 1.8 $ Date Last Revised: $Date: 1995/08/03 15:59:17 $ Description of Problem ---------------------- In an aggregate that includes a named association, it is not clear how many times the value expression is evaluated if the choice covers more than one element. The value expression could be evaluated once and the resulting value applied for each element or the value expression could be evaluated once for each element. The distinction is important in cases such as (1 to 10 => new INTEGER). Are 10 allocations performed or one? In Ada, the value expression is evaluated once for each element, giving 10 allocations in this example. Since most of the aggregate semantics in VHDL are taken directly from Ada, the Ada interpretation is probably what is intended. Proposed Resolution ------------------- The value expression of a named association appearing in an aggregate is evaluated once for each associated element. VASG-ISAC Analysis & Rationale ------------------------------ TBD VASG-ISAC Recommendation for IEEE Std 1076-1987 ----------------------------------------------- TBD VASG-ISAC Recommendation for Future Revisions --------------------------------------------- TBD