VHDL Issue Number:      0047
Classification:         Language Definition Problem
Language Version:       VHDL-87
Summary:                Multiple meanings for a selected name prefix are not
                        well defined.
Related Issues:         0006, 0108, 0109
Relevant LRM Sections:  6.3
Key Words and Phrases:  Selected name, overloading, prefix
Current Status:         Analyzed
1076-1993 Disposition:  Closed (All Issues Completely Addressed)
Disposition Rationale:  LRM covers this.
Superseded By:          N/A
-----------------------
Date Submitted:         1989/02/10
Author of Submission:   Doug Dunlop
Author's Affiliation:   Intermetrics, Inc.
Author's Post Address:  4733 Bethesda Ave #415
                        Bethesda, MD  20814
Author's Phone Number:  (301) 657-3775
Author's Fax Number:    
Author's Net Address:   dunlop@inmet.inmet.com
-----------------------
Date Analyzed:          1991/01/18
Author of Analysis:     Paul Menchini (mench@clsi.com)
Revision Number:        $Revision: 1.10 $
Date Last Revised:      $Date: 1995/08/03 15:59:40 $


Description of Problem
----------------------
There are two aspects to this problem.  First, consider

         function f return bit is
            x : integer;
            function f return boolean is
               function f return integer is
                  x : real;
               begin
                  ... f.x ...
               end f;
            ...
            end f;
         ...
         end f;

Is the selected name "f.x" illegal?  If not, what does it mean?  Is it legal
provided the context requires either integer or real, with the context
determining which x is selected?  Unlike the Ada LRM, the VHDL LRM does not
explicitly declare this to be illegal.  Second, consider the following

        type r is record f : integer; end record;
        function x return r is
           variable f : integer;
           variable v : integer;
        begin
           v := x.f;
           ...
        end x;

Is the selected name "x.f" illegal?  If not, what does it mean?  Unlike the Ada
LRM, the VHDL LRM does not explicitly define the meaning of this case.  In Ada,
the "expanded name" interpretation (i.e., "x.f" means the local variable f
declared inside x) has precedence.


Proposed Resolution
-------------------
These appear to be cases that were overlooked when subprogram overloading was
added to the language.  The Ada interpretation of these cases seems natural and
that is what we assume.


VASG-ISAC Analysis & Rationale
------------------------------
This issue was considered together with issues 6, 108, and 109.  The analysis,
rationale, 1987 recommendation and future recommendation sections of Issue 6
apply equally to this issue.


VASG-ISAC Recommendation for IEEE Std 1076-1987
-----------------------------------------------
See Issue Report 0006.


VASG-ISAC Recommendation for Future Revisions
---------------------------------------------
See Issue Report 0006.