VHDL Issue Number:      0050
Classification:         Language Definition Problem
Language Version:       VHDL-87
Summary:                No meaning for the direction of an aggregate
                        discrete-range choice.
Related Issues:         
Relevant LRM Sections:  7.3.2, 3.2.1.1
Key Words and Phrases:  Aggregate, choice, discrete range
Current Status:         ISAC-Approved
1076-1993 Disposition:  Closed (All Issues Completely Addressed)
Disposition Rationale:  VHDL-93 LRM was updated.
Superseded By:          N/A
-----------------------
Date Submitted:         1989/02/10
Author of Submission:   Doug Dunlop
Author's Affiliation:   Intermetrics, Inc.
Author's Post Address:  4733 Bethesda Ave #415
                        Bethesda, MD  20814
Author's Phone Number:  (301) 657-3775
Author's Fax Number:    
Author's Net Address:   dunlop@inmet.inmet.com
-----------------------
Date Analyzed:          1990/09/27
Author of Analysis:     Alex Zamfirescu 
Revision Number:        $Revision: 1.9 $
Date Last Revised:      $Date: 1995/08/03 00:29:43 $

Revision Number:        $Revision: 1.9 $
Date Last Revised:      $Date: 1995/08/03 00:29:43 $


Description of Problem
----------------------
What is the meaning of the direction of a discrete
range that appears in an aggregate?


Proposed Resolution
-------------------
It is of no significance.  The discrete range in this context
merely defines a set of index values.  The choices 1 TO 2 and 2 DOWNTO 1 are
equivalent in an aggregate.


VASG-ISAC Analysis & Rationale
------------------------------
First, the rules from LRM 7.3.2 

        aggregate ::=
           (element_association { , element_association})

        element_association ::=
           [choices => ] expression

        choices ::= choice { | choice }

        choice ::=
           simple_expression
           | discrete_range
           | ELEMENT_simple_name
           | others 

make an aggrgate invariant to the direction of a discrete range since by 
the second rule above, the same expression is associated for all choices in
an element association. 

Second, the last paragraph in LRM 7.3.2 clearly states that the type of an 
aggregate must be determinable solely from the context in which the aggregate
appears, excluding the aggregate itself. This forbids the use of a discrete 
range direction to determine the aggregate type. 

Third, flagging an error for a mismatch in direction is meaningless.

The natural conclusion is to ignore the direction of a discrete range that 
appears in an aggregate. 

Note: The subtype of an aggregate is an undefined concept in the 
LRM (see second paragraph of VASG-ISAC Analysis & Rationale for IR0080)
However, ignoring the direction of a discrete range that appears in an
aggregate should not be interpreted as if the hole discrete range has 
no type significance. Only the direction can be ignored.
Example 2 of IR0080

   2. The aggregate provides subtype information, the context does not:
        "constant C: bit_vector := (7 downto 0 => '0');

should be interpreted as defining an ascending bit_vector (0 to 7).


VASG-ISAC Recommendation for IEEE Std 1076-1987
-----------------------------------------------
The intent of the language is to allow any direction of a discrete
range that appears in an aggregate. The direction of a discrete range
is used in an aggregate just to express a correct discrete range,
and it has no other significance.


VASG-ISAC Recommendation for Future Revisions
---------------------------------------------
Add clarification to LRM. 
If a future language version will contain a set_specification, then defining
choices above as such a set, where order is explicitly meaningless, will also
solve the problem.