VHDL Issue Number:      0062
Classification:         Language Definition Problem
Language Version:       VHDL-87
Summary:                Concatenation is incompletely defined for arrays of
                        arrays.
Related Issues:         
Relevant LRM Sections:  7.2.3   
Key Words and Phrases:  Concatenation, array
Current Status:         ISAC-Approved
1076-1993 Disposition:  Closed (All Issues Completely Addressed)
Disposition Rationale:  7.2.4 (VHDL-93 LRM) was updated.
Superseded By:          N/A
-----------------------
Date Submitted:         1989/02/10
Author of Submission:   Doug Dunlop
Author's Affiliation:   Intermetrics, Inc.
Author's Post Address:  4733 Bethesda Ave #415
                        Bethesda, MD  20814
Author's Phone Number:  (301) 657-3775
Author's Fax Number:    
Author's Net Address:   dunlop@inmet.inmet.com
-----------------------
Date Analyzed:          1990/06/14
Author of Analysis:     Doug Dunlop
Revision Number:        $Revision: 1.10 $
Date Last Revised:      $Date: 1995/08/03 16:00:54 $


Description of Problem
----------------------
If T1 is a 1-dimensional array type and type T2 is a
1-dimensional array of T1, what does it mean to concatenate a value of type
T1 with a value of type T2?  This is allowed according to the table in LRM
Section 7.2.3 (the third concatenation entry applies).  However, the result
defined in Case 1 following the table is absurd in this situation (even though
both are one-dimensional arrays) since the operands are not of the same type.


Proposed Resolution
-------------------
It is probably intended that this be allowed; it is the
description of the result in LRM 7.2.3 that is flawed.  We accordingly allow
the kind of concatenation described above and interpret the result as described
in Case 2 (instead of as in Case 1).


VASG-ISAC Analysis & Rationale
------------------------------
Indeed, the Language Definition Problem is flawed as stated above.  In addition, it
does not properly cover the case of concatenating two one-dimensional arrays
where both operands are the element type (e.g., concatenating two objects of
type T1 as defined above).


VASG-ISAC Recommendation for IEEE Std 1076-1987
-----------------------------------------------
The "three case" list in LRM 7.2.3 should be replaced by a semantic definition
of each of the four operators associated with concatenation.  These four
operators correspond to the four entries in the table (above the list)
for the concatenation operation.  This description of the four operators
should not imply a "priority" among these operators and should not attempt to
explicitly identify, for any concatenation operation, which of the four
operators applies.   As an aid to the reader, a "Note:" should be
added to this section stating that the applicable operator for any
concatenation operation is determined by the normal overloading rules of the
language.

A consequence of this interpretation of VHDL is that the following declarations
are legal:

   subtype Byte is Bit_Vector(1 to 8);
   type Memory is array(Natural range <>) of Byte;
   constant Zero_Byte: Byte := B"00000000";
   type Matrix is array(Natural range <>) of Memory(1 to 2);

   constant C1 : Memory     := Zero_Byte & Zero_Byte;
   constant C2 : Memory     := C1        & Zero_Byte;
   constant C3 : Memory     := Zero_Byte & C1       ;
   constant C4 : Memory     := C1        & C1       ;

   constant C5 : Bit_Vector := Zero_Byte & Zero_Byte;
   constant C6 : Matrix     := C1        & C1       ;


VASG-ISAC Recommendation for Future Revisions
---------------------------------------------
Put in the correct LRM wording to achieve the effect as stated above.