VHDL Issue Number:      0065
Classification:         Language Definition Problem
Language Version:       VHDL-87
Summary:                Ambiguous visibility of block specification in a block
                        configuration.
Related Issues:         
Relevant LRM Sections:  1.3.2
Key Words and Phrases:  Block configuration, component configuration,
                        visibility
Current Status:         ISAC-Approved
1076-1993 Disposition:  Closed (All Issues Completely Addressed)
Disposition Rationale:  LRM was updated.
Superseded By:          N/A
-----------------------
Date Submitted:         1989/02/10
Author of Submission:   Doug Dunlop
Author's Affiliation:   Intermetrics, Inc.
Author's Post Address:  4733 Bethesda Ave #415
                        Bethesda, MD  20814
Author's Phone Number:  (301) 657-3775
Author's Fax Number:    
Author's Net Address:   dunlop@inmet.inmet.com
-----------------------
Date Analyzed:          1990/06/15
Author of Analysis:     Doug Dunlop
Revision Number:        $Revision: 1.10 $
Date Last Revised:      $Date: 1995/08/03 16:27:22 $


Description of Problem
----------------------
Consider the following VHDL

      architecture A of E is
         component C end component;
         for L1 : C use entity E1(X);
         for L2 : C use entity E2(X);
      begin
         L1 : C;
         L2 : C;
      end A;
      ------
      configuration C of E is
         for A
            for L1, L2 : C
               for X
                  ...
               end for;
            end for;
         end for;
      end C;

Which architecture body is referenced by the "X" in the inner block
configuration of the configuration?  This is clearly an error situation.  


Proposed Resolution
-------------------
If a component configuration contains an explicit block
configuration, then the corresponding component instances must be bound
to the same architecture body.


VASG-ISAC Analysis & Rationale
------------------------------
The resolution proposed by the submitter seems quite reasonable.  It
is difficult to imagine doing conventional analysis-time processing
(e.g., associating references with declared items) on an inner block
configuration without this restriction.

A lone dissenter on the ISAC suggested it was too constraining on
implementations to declare the above case to be an error.  The view
here is that it is desirable to allow configurations to be processed
in an interpretive fashion at elaboration time.  In this light, the
configuration information from the above example

      for X
         ...
      end for;

is "interpreted" multiple times, once for the instance labeled L1 and
once for the instance labeled L2.  If this configuration information
is going to be interpreted once for each instance, there is really no
need to require that the instances be bound to the same architecture
body.


VASG-ISAC Recommendation for IEEE Std 1076-1987
-----------------------------------------------
As suggested above under "Proposed Resolution".


VASG-ISAC Recommendation for Future Revisions
---------------------------------------------