VHDL Issue Number: 0072 Classification: Language Definition Problem Language Version: VHDL-87 Summary: Reference to a generate loop parameter in a configuration is unclear. Related Issues: 0027, 0029, 0112 Relevant LRM Sections: 9.7, 1.3 Key Words and Phrases: Generate loop parameter, configuration declaration Current Status: Submitted 1076-1993 Disposition: Superseded (ISAC Issues Outstanding) Disposition Rationale: N/A Superseded By: 1013 ----------------------- Date Submitted: 1989/02/10 Author of Submission: Doug Dunlop Author's Affiliation: Intermetrics, Inc. Author's Post Address: 4733 Bethesda Ave #415 Bethesda, MD 20814 Author's Phone Number: (301) 657-3775 Author's Fax Number: Author's Net Address: dunlop@inmet.inmet.com ----------------------- Date Analyzed: TBD Author of Analysis: TBD Revision Number: $Revision: 1.10 $ Date Last Revised: $Date: 1995/05/13 21:53:48 $ Description of Problem ---------------------- References to generate loop parameters from within a configuration are not defined. As an example, consider architecture arch of e is begin b: for i in 1 to 10 generate ... end generate; end arch; configuration c of e is for arch for b(i) ... end for; end for; end c; Is the configuration valid? If so, what does it mean? The problem specifically is that the point in the elaboration process at which "b(i)" gets evaluated is not specified. Proposed Resolution ------------------- Rather than disallowing this, it seems to make more sense to say that the corresponding block specification(s) are elaborated each time the body of the generate statement is elaborated. Hence the above for b(i) ... is equivalent to for b ... i.e., means "for all". VASG-ISAC Analysis & Rationale ------------------------------ TBD VASG-ISAC Recommendation for IEEE Std 1076-1987 ----------------------------------------------- TBD VASG-ISAC Recommendation for Future Revisions --------------------------------------------- TBD