VHDL Issue Number: 0073 Classification: Language Definition Problem Language Version: VHDL-87 Summary: Use of block configurations with mixed generates and blocks unclear. Related Issues: Relevant LRM Sections: 1.3.1 Key Words and Phrases: Generate statements, block configurations Current Status: Submitted 1076-1993 Disposition: Closed (All Issues Completely Addressed) Disposition Rationale: Now have declarative region for generates. Superseded By: N/A ----------------------- Date Submitted: 1989/02/10 Author of Submission: Doug Dunlop Author's Affiliation: Intermetrics, Inc. Author's Post Address: 4733 Bethesda Ave #415 Bethesda, MD 20814 Author's Phone Number: (301) 657-3775 Author's Fax Number: Author's Net Address: dunlop@inmet.inmet.com ----------------------- Date Analyzed: TBD Author of Analysis: TBD Revision Number: $Revision: 1.8 $ Date Last Revised: $Date: 1995/08/03 17:15:49 $ Description of Problem ---------------------- The LRM allows block configurations to apply to generate statements. It is unclear what the rules are for using block configurations when the corresponding architecture body has mixed and nested block statements and generate statements. The confusion is due to the use of the phrases "the block", "the given block", and "within a given block" in the paragraph beginning "If a block configuration appears immediately wihin another ..." and the paragraphs beginning "For any name ..." of LRM 1.3.1. To make sense and to be consistent, "block" here should mean "block statement or generate statement". Similarly "within" in these paragraphs should be taken to mean "immediately within". Proposed Resolution ------------------- The above interpretation of these paragraphs is assumed. Thus these paragraphs are read as (with changes in upper case): If a block configuration appears immediately within another block configuration, then the block specification of the contained block configuration must be a block statement or generate statment label, and the label must denote a block statement or generate statement that is contained immediately within the BLOCK STATEMENT OR GENERATE STATEMENT denoted by the block specification of the containing block configuration. For any name that is the label of a block statement appearing IMMEDIATELY WITHIN a given BLOCK STATEMENT OR GENERATE STATEMENT, a corresponding block configuration may appear as a configuration item IMMEDIATELY WITHIN a block configuration corresponding to the given BLOCK STATEMENT OR GENERATE STATEMENT. For any collection of names that are labels of instances of the same component appearing IMMEDIATELY WITHIN a given BLOCK STATEMENT OR GENERATE STATEMENT, a corresponding component configuration may appear as a configuration item IMMEDIATELY WITHIN a block configuration corresponding to the given BLOCK STATEMENT OR GENERATE STATEMENT. For any name that is the label of a generate statement IMMEDIATELY WITHIN a given BLOCK STATEMENT OR GENERATE STATEMENT, one or more corresponding block configurations may appear as configuration items IMMEDIATELY WITHIN a block configuration corresponding to the given BLOCK STATEMENT OR GENERATE STATEMENT. ... To illustrate this, consider the following entity and architecture definition: entity E is generic(N : Positive); port(P : out Bit); end E; -------------------------------------------------------------------------------- use Work.E; architecture A of E is begin G1 : if N > 1 generate L:block signal S : Bit; component C generic(N : Positive); port(P : out Bit); end component; begin I:C generic map(N => N - 1) port map(P => S); P <= not S; end block; end generate; G2 : if N = 1 generate P <= '0'; end generate; end A; To write a component configuration that applies to the statement labelled "I", this component configuration must be contained in a block configuration that applies to block "L" that in turn must be contained in a block configuration that applies to generate statement "G1" as in use Work.E; configuration C1 of E is for A for G1 for L for I : C use entity E(A); end for; end for; end for; end for; end C1; VASG-ISAC Analysis & Rationale ------------------------------ TBD VASG-ISAC Recommendation for IEEE Std 1076-1987 ----------------------------------------------- TBD VASG-ISAC Recommendation for Future Revisions --------------------------------------------- TBD